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From: "Darren Pilgrim" <darren.pilgrim@bitfreak.org>
To: "'John Baldwin'" <jhb@freebsd.org>, <freebsd-current@freebsd.org>
Date: Wed, 7 Dec 2005 15:11:41 -0800
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Subject: RE: can someone explain...[ PCI interrupts]
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From: John Baldwin
>=20
> No, PCI interrupts are level triggered.  Individual APIC pins
> can be programmed to be edge-triggered, sure.  However, then
> interrupts stop working if 2 devices are sharing a line and
> one interrupts after the other has already interrupted and
> after the second device's ISR has already run.  In this case,
> the ithread will finish and go back to sleep waiting for an
> interrupt.  However, since the ISR for the second device
> wasn't run after that device asserted its interrupt pin, the
> second device will keep the pin pulled low forever, so there
> will never be a hi -> low transition that the APIC pin would
> post an interrupt for and that intpin and all attached
> devices are effectively dead.

What if the APIC was programmed to be edge-triggered just before the =
ithread
runs and programmed back to level-trigger when the ithread completes?