From owner-svn-src-all@FreeBSD.ORG Mon Mar 5 06:41:45 2012 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 7590A1065678; Mon, 5 Mar 2012 06:41:45 +0000 (UTC) (envelope-from hselasky@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 560BB8FC12; Mon, 5 Mar 2012 06:41:45 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id q256fjvS071144; Mon, 5 Mar 2012 06:41:45 GMT (envelope-from hselasky@svn.freebsd.org) Received: (from hselasky@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id q256fjk2071140; Mon, 5 Mar 2012 06:41:45 GMT (envelope-from hselasky@svn.freebsd.org) Message-Id: <201203050641.q256fjk2071140@svn.freebsd.org> From: Hans Petter Selasky Date: Mon, 5 Mar 2012 06:41:45 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r232539 - head/sys/dev/usb/controller X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 05 Mar 2012 06:41:45 -0000 Author: hselasky Date: Mon Mar 5 06:41:44 2012 New Revision: 232539 URL: http://svn.freebsd.org/changeset/base/232539 Log: Fix for DWC OTG interrupt register programming. Fix a compiler warning. Add missing header file. MFC after: 1 week Modified: head/sys/dev/usb/controller/dwc_otg.c head/sys/dev/usb/controller/dwc_otg.h head/sys/dev/usb/controller/dwc_otg_atmelarm.c Modified: head/sys/dev/usb/controller/dwc_otg.c ============================================================================== --- head/sys/dev/usb/controller/dwc_otg.c Mon Mar 5 06:12:15 2012 (r232538) +++ head/sys/dev/usb/controller/dwc_otg.c Mon Mar 5 06:41:44 2012 (r232539) @@ -91,6 +91,7 @@ __FBSDID("$FreeBSD$"); #define DWC_OTG_MSK_GINT_ENABLED \ (DWC_OTG_MSK_GINT_ENUM_DONE | \ + DWC_OTG_MSK_GINT_USB_RESET | \ DWC_OTG_MSK_GINT_USB_SUSPEND | \ DWC_OTG_MSK_GINT_INEP | \ DWC_OTG_MSK_GINT_RXFLVL | \ @@ -730,7 +731,10 @@ repeat: } } - /* check if no packets have been transferred */ + if (!to--) + goto not_complete; + + /* check if not all packets have been transferred */ temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DIEPTSIZ(td->ep_no)); if (DWC_OTG_MSK_DXEPTSIZ_GET_NPKT(temp) != 0) { @@ -812,9 +816,7 @@ repeat: /* else we need to transmit a short packet */ } - - if (--to) - goto repeat; + goto repeat; not_complete: return (1); /* not complete */ @@ -927,7 +929,6 @@ repeat: if (sc->sc_last_rx_status != 0) { - uint32_t temp; uint8_t ep_no; temp = DWC_OTG_MSK_GRXSTS_GET_BYTE_CNT( @@ -1042,6 +1043,18 @@ dwc_otg_interrupt(struct dwc_otg_softc * DPRINTFN(14, "GINTSTS=0x%08x\n", status); + if (status & DWC_OTG_MSK_GINT_USB_RESET) { + + /* set correct state */ + sc->sc_flags.status_bus_reset = 0; + sc->sc_flags.status_suspend = 0; + sc->sc_flags.change_suspend = 0; + sc->sc_flags.change_connect = 1; + + /* complete root HUB interrupt endpoint */ + dwc_otg_root_intr(sc); + } + /* check for any bus state change interrupts */ if (status & DWC_OTG_MSK_GINT_ENUM_DONE) { @@ -1115,6 +1128,7 @@ dwc_otg_interrupt(struct dwc_otg_softc * } /* check VBUS */ if (status & (DWC_OTG_MSK_GINT_USB_SUSPEND | + DWC_OTG_MSK_GINT_USB_RESET | DWC_OTG_MSK_GINT_SESSREQINT)) { uint32_t temp; @@ -1133,9 +1147,10 @@ dwc_otg_interrupt(struct dwc_otg_softc * for (x = 0; x != sc->sc_dev_in_ep_max; x++) { temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_DIEPINT(x)); - if (temp == 0) - continue; - DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPINT(x), temp); + if (temp & DWC_OTG_MSK_DIEP_XFER_COMPLETE) { + DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPINT(x), + DWC_OTG_MSK_DIEP_XFER_COMPLETE); + } } } @@ -1773,17 +1788,25 @@ dwc_otg_init(struct dwc_otg_softc *sc) sc->sc_irq_mask = DWC_OTG_MSK_GINT_ENABLED; DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GINTMSK, sc->sc_irq_mask); - /* - * Disable all endpoint interrupts, - * we use the SOF IRQ for transmit: - */ - /* enable all endpoint interrupts */ - DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPMSK, - /* DWC_OTG_MSK_DIEP_FIFO_EMPTY | */ - DWC_OTG_MSK_DIEP_XFER_COMPLETE); - DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPMSK, 0); - DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DAINTMSK, 0xFFFF); + temp = DWC_OTG_READ_4(sc, DWC_OTG_REG_GHWCFG2); + if (temp & DWC_OTG_MSK_GHWCFG2_MPI) { + uint8_t x; + + DPRINTF("Multi Process Interrupts\n"); + + for (x = 0; x != sc->sc_dev_in_ep_max; x++) { + DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPEACHMSK(x), + DWC_OTG_MSK_DIEP_XFER_COMPLETE); + DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPEACHMSK(x), 0); + } + DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DEACHINTMSK, 0xFFFF); + } else { + DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DIEPMSK, + DWC_OTG_MSK_DIEP_XFER_COMPLETE); + DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DOEPMSK, 0); + DWC_OTG_WRITE_4(sc, DWC_OTG_REG_DAINTMSK, 0xFFFF); + } /* enable global IRQ */ DWC_OTG_WRITE_4(sc, DWC_OTG_REG_GAHBCFG, Modified: head/sys/dev/usb/controller/dwc_otg.h ============================================================================== --- head/sys/dev/usb/controller/dwc_otg.h Mon Mar 5 06:12:15 2012 (r232538) +++ head/sys/dev/usb/controller/dwc_otg.h Mon Mar 5 06:41:44 2012 (r232539) @@ -140,6 +140,8 @@ #define DWC_OTG_REG_GHWCFG2 0x0048 #define DWC_OTG_MSK_GHWCFG2_NUM_DEV_EP(x) ((((x) >> 10) & 15) + 1) #define DWC_OTG_MSK_GHWCFG2_NUM_HOST_EP(x) ((((x) >> 14) & 15) + 1) +#define DWC_OTG_MSK_GHWCFG2_DYN_FIFO (1U << 19) +#define DWC_OTG_MSK_GHWCFG2_MPI (1U << 20) #define DWC_OTG_REG_GHWCFG3 0x004C #define DWC_OTG_MSK_GHWCFG3_GET_DFIFO(x) ((x) >> 16) #define DWC_OTG_MSK_GHWCFG3_PKT_SIZE (0x10U << (((x) >> 4) & 7)) @@ -245,11 +247,7 @@ #define DWC_OTG_REG_DEACHINT 0x0838 #define DWC_OTG_REG_DEACHINTMSK 0x083C #define DWC_OTG_REG_DIEPEACHMSK(n) (0x0840 + (4*(n))) -#define DWC_OTG_MSK_DIEPEACH_XFER_COMPLETE (1U << 0) - #define DWC_OTG_REG_DOEPEACHMSK(n) (0x0880 + (4*(n))) -#define DWC_OTG_MSK_DOEPEACH_SETUP (1U << 3) -#define DWC_OTG_MSK_DOEPEACH_XFER_COMPLETE (1U << 0) #define DWC_OTG_REG_DIEPCTL(n) (0x0900 + (32*(n))) #define DWC_OTG_MSK_DIEPCTL_ENABLE (1U << 31) Modified: head/sys/dev/usb/controller/dwc_otg_atmelarm.c ============================================================================== --- head/sys/dev/usb/controller/dwc_otg_atmelarm.c Mon Mar 5 06:12:15 2012 (r232538) +++ head/sys/dev/usb/controller/dwc_otg_atmelarm.c Mon Mar 5 06:41:44 2012 (r232539) @@ -44,6 +44,7 @@ __FBSDID("$FreeBSD$"); #include #include #include +#include #include #include