From owner-freebsd-arch@FreeBSD.ORG Sun Sep 26 19:28:53 2010 Return-Path: Delivered-To: freebsd-arch@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id DA135106564A for ; Sun, 26 Sep 2010 19:28:53 +0000 (UTC) (envelope-from paketix@bluewin.ch) Received: from mail31.bluewin.ch (mail31.bluewin.ch [195.186.18.72]) by mx1.freebsd.org (Postfix) with ESMTP id 710458FC14 for ; Sun, 26 Sep 2010 19:28:53 +0000 (UTC) Received: from [195.186.18.84] ([195.186.18.84:40549] helo=tr17.bluewin.ch) by mail31.bluewin.ch (envelope-from ) (ecelerity 2.2.2.45 r()) with ESMTP id DB/E9-19667-4FE9F9C4; Sun, 26 Sep 2010 19:28:52 +0000 Received: from [192.168.1.62] (188.61.142.81) by tr17.bluewin.ch (The Blue Window 8.5.119.018.5.119.01) (authenticated as paketix@bluewin.ch) id 4C6921000184B737; Sun, 26 Sep 2010 19:28:52 +0000 Mime-Version: 1.0 (Apple Message framework v1081) Content-Type: text/plain; charset=us-ascii From: Paketix In-Reply-To: Date: Sun, 26 Sep 2010 21:28:51 +0200 Content-Transfer-Encoding: quoted-printable Message-Id: <616133A7-3DF8-4192-8457-09BC27D2085E@bluewin.ch> References: To: Garrett Cooper X-Mailer: Apple Mail (2.1081) Cc: freebsd-arch@freebsd.org Subject: Re: Porting effort towards TILERA massive multicore CPUs...? X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 26 Sep 2010 19:28:54 -0000 On Sep 26, 2010, at 20:05, Garrett Cooper wrote: > On Sun, Sep 26, 2010 at 4:13 AM, Paketix wrote: >> there is a rather new processor from TILERA (100 core chip) which is >> most certainly already known here at FreeBSD mailing list. >> [http://www.tilera.com/products/processors/TILE-Gx_Family] >> the processor/platform is targeted towards: >> - high performance network security platforms >> - firewalling/vpn >> - utm >> - l7 deep packet inspection >> - network monitoring and forensics >> - cloud computing >> - web application (lamp) >> - data caching (memcached) >> - database applications >> - high-performance computing >>=20 >> chris metcalf from TILERA did the current linux port and i was in >> contact with him about two weeks ago. >> at this time QUANTA computer is starting to offer a 512 core 2U box >> with an impressive performance/watt ratio (400 watts only for 512 >> cores). >> [http://www.tilera.com/solutions/cloud_computing] >>=20 >> i guess those massive multicore chips would enable bleeding edge >> high performance solutions based on FreeBSD. >>=20 >> well... >> - anyone interested in porting FreeBSD towards TILERA? >> (architecture seems to be similar to MIPS...) >> - is there already some ongoing porting effort? >> - porting for this chip already discussed in this mailing list? >>=20 >> many thx >> /pat >>=20 >> some links for those who want some more details: >> company homepage: >> http://www.tilera.com/ >> 64core processor: >> http://www.tilera.com/products/processors/TILEPRO64 >> 100core processor with hardware packet (pre)processing >> http://www.tilera.com/products/processors/TILE-Gx_Family >> sample architecture for network appliances: >> = http://www.tilera.com/solutions/networking/network_security_appliances >> 512core system from QUANTA computer inc. (available Q4-10/Q1-11): >> http://www.tilera.com/solutions/cloud_computing >> development system from TILERA: >> http://www.tilera.com/products/platforms/TILEmpower_platform >=20 > In short this work requires changes to the scheduler and kernel > structures that aren't 100% done yet. Look for some of Robert Watson > and John Baldwin's replies to "Bumping MAXCPU on amd64" thread in the > past month to freebsd-arch and freebsd-current. > Cheers, > -Garrett usually it would - yes but maybe not on tilera if you use it for security applications (like = firewalling, proxy, url filter, ...) each tile of a tilera chip chan run its own full featured OS starting with TileGX the chip has a hardware loadbalancer serving the = packet streams to the cores... this could maybe serve as a first step full SMP for e.g. database applications etc. later on btw: the tilera chip does not have a floating point unit anyway which = will limit the range of applications (FP must be emulated in software) BR /pat=