From owner-freebsd-arch@FreeBSD.ORG Tue Jul 25 15:13:14 2006 Return-Path: X-Original-To: freebsd-arch@freebsd.org Delivered-To: freebsd-arch@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 674BE16A51C for ; Tue, 25 Jul 2006 15:13:14 +0000 (UTC) (envelope-from asmrookie@gmail.com) Received: from wx-out-0102.google.com (wx-out-0102.google.com [66.249.82.199]) by mx1.FreeBSD.org (Postfix) with ESMTP id AEA6343D45 for ; Tue, 25 Jul 2006 15:13:13 +0000 (GMT) (envelope-from asmrookie@gmail.com) Received: by wx-out-0102.google.com with SMTP id i31so976848wxd for ; Tue, 25 Jul 2006 08:13:13 -0700 (PDT) DomainKey-Signature: a=rsa-sha1; q=dns; c=nofws; s=beta; d=gmail.com; h=received:message-id:date:from:sender:to:subject:cc:mime-version:content-type:content-transfer-encoding:content-disposition:x-google-sender-auth; b=P2EVHfsFDdJWzxFj9Zec/KTAwcbyaqtlAIzVPyTxvF4S5lSFBnRxm8gE0ltxne5zGMMQ272qRVSX8+58VGbxPO96jGKbQSpmwjA+71cD0y/8Qnj238gG+c1LxfrzWsnnyzAxdD5xFPiV5dJa2KrgWizWJuLlqGeu6/Ey7RyEdBw= Received: by 10.70.44.5 with SMTP id r5mr820589wxr; Tue, 25 Jul 2006 08:13:12 -0700 (PDT) Received: by 10.70.11.18 with HTTP; Tue, 25 Jul 2006 08:13:12 -0700 (PDT) Message-ID: <3bbf2fe10607250813w8ff9e34pc505bf290e71758@mail.gmail.com> Date: Tue, 25 Jul 2006 17:13:12 +0200 From: "Attilio Rao" Sender: asmrookie@gmail.com To: freebsd-arch@freebsd.org MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Content-Disposition: inline X-Google-Sender-Auth: cc91b2f89e4d364c Cc: Subject: [PATCH] Mantaining turnstile aligned to 128 bytes in i386 CPUs X-BeenThere: freebsd-arch@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussion related to FreeBSD architecture List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 25 Jul 2006 15:13:14 -0000 Hi, Intel documentation points out that having a 128-bytes aligned syncronizing primitive (which fits in a cache line) will minimize the traffic for cache bus, so this patch implements an alignment for i386 on turnstiles. Any comments, feedbacks? Attilio PS: Using __aligned on MI code is usually a bad practice, but please note that the case !__i386__ is not affected (as you can see in the patch) -- Peace can only be achieved by understanding - A. Einstein