From owner-freebsd-hackers@FreeBSD.ORG Fri Oct 10 06:44:08 2003 Return-Path: Delivered-To: freebsd-hackers@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 4028A16A4B3; Fri, 10 Oct 2003 06:44:08 -0700 (PDT) Received: from arginine.spc.org (arginine.spc.org [195.206.69.236]) by mx1.FreeBSD.org (Postfix) with ESMTP id EC33043FDD; Fri, 10 Oct 2003 06:44:03 -0700 (PDT) (envelope-from bms@spc.org) Received: from localhost (localhost [127.0.0.1]) by arginine.spc.org (Postfix) with ESMTP id 3814B654F9; Fri, 10 Oct 2003 14:44:02 +0100 (BST) Received: from arginine.spc.org ([127.0.0.1]) by localhost (arginine.spc.org [127.0.0.1]) (amavisd-new, port 10024) with LMTP id 77681-01-3; Fri, 10 Oct 2003 14:44:01 +0100 (BST) Received: from saboteur.dek.spc.org (unknown [81.3.72.68]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by arginine.spc.org (Postfix) with ESMTP id 8B57C654F7; Fri, 10 Oct 2003 14:44:01 +0100 (BST) Received: by saboteur.dek.spc.org (Postfix, from userid 1001) id BB2295; Fri, 10 Oct 2003 14:44:00 +0100 (BST) Date: Fri, 10 Oct 2003 14:44:00 +0100 From: Bruce M Simpson To: Joseph Koshy Message-ID: <20031010134400.GE803@saboteur.dek.spc.org> Mail-Followup-To: Joseph Koshy , freebsd-hackers@freebsd.org References: <20031010103640.6F5A216A4BF@hub.freebsd.org> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable In-Reply-To: <20031010103640.6F5A216A4BF@hub.freebsd.org> cc: freebsd-hackers@freebsd.org Subject: Re: Determining CPU features / cache organization from userland X-BeenThere: freebsd-hackers@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Technical Discussions relating to FreeBSD List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 10 Oct 2003 13:44:08 -0000 On Fri, Oct 10, 2003 at 03:36:40AM -0700, Joseph Koshy wrote: > I'm looking for ways that a userland program can determine the CPU > features available on an SMP machine -- processor model, stepping > numbers, supported features, cache organization etc. "What Silby said" and have a look at the sysutils/x86info port. I've been thinking we should definitely make the cache organization info available via sysctl. I am thinking we should do this to make the UMA_ALIGN_CACHE definition mean something... I will probably throw diffs Jeff's way soon for this but I'm recovering =66rom a bit of a nasty cold right now. BMS