From owner-svn-src-stable@FreeBSD.ORG Fri Nov 1 21:17:47 2013 Return-Path: Delivered-To: svn-src-stable@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id E09A7A94; Fri, 1 Nov 2013 21:17:46 +0000 (UTC) (envelope-from brooks@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:1900:2254:2068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id CC52928E5; Fri, 1 Nov 2013 21:17:46 +0000 (UTC) Received: from svn.freebsd.org ([127.0.1.70]) by svn.freebsd.org (8.14.7/8.14.7) with ESMTP id rA1LHkA3055692; Fri, 1 Nov 2013 21:17:46 GMT (envelope-from brooks@svn.freebsd.org) Received: (from brooks@localhost) by svn.freebsd.org (8.14.7/8.14.5/Submit) id rA1LHkG9055688; Fri, 1 Nov 2013 21:17:46 GMT (envelope-from brooks@svn.freebsd.org) Message-Id: <201311012117.rA1LHkG9055688@svn.freebsd.org> From: Brooks Davis Date: Fri, 1 Nov 2013 21:17:46 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-10@freebsd.org Subject: svn commit: r257528 - in stable/10/sys: conf mips/beri mips/include mips/mips X-SVN-Group: stable-10 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for all the -stable branches of the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 Nov 2013 21:17:47 -0000 Author: brooks Date: Fri Nov 1 21:17:45 2013 New Revision: 257528 URL: http://svnweb.freebsd.org/changeset/base/257528 Log: MFC r256935 MFP4: Change 228019 by bz@bz_zenith on 2013/04/23 13:55:30 Add kernel side support for large TLB on BERI/CHERI. Modelled similar to NLM Sponsored by: DAPRA/AFRL Approved by: re (delphij) Modified: stable/10/sys/conf/options.mips stable/10/sys/mips/beri/std.beri stable/10/sys/mips/include/cpufunc.h stable/10/sys/mips/mips/cpu.c Directory Properties: stable/10/sys/ (props changed) stable/10/sys/conf/ (props changed) Modified: stable/10/sys/conf/options.mips ============================================================================== --- stable/10/sys/conf/options.mips Fri Nov 1 21:15:39 2013 (r257527) +++ stable/10/sys/conf/options.mips Fri Nov 1 21:17:45 2013 (r257528) @@ -81,6 +81,11 @@ OCTEON_VENDOR_GEFES opt_cvmx.h OCTEON_BOARD_CAPK_0100ND opt_cvmx.h # +# Options specific to the BERI platform. +# +BERI_LARGE_TLB opt_global.h + +# # Options that control the Atheros SoC peripherals # ARGE_DEBUG opt_arge.h Modified: stable/10/sys/mips/beri/std.beri ============================================================================== --- stable/10/sys/mips/beri/std.beri Fri Nov 1 21:15:39 2013 (r257527) +++ stable/10/sys/mips/beri/std.beri Fri Nov 1 21:17:45 2013 (r257528) @@ -2,3 +2,5 @@ files "../beri/files.beri" cpu CPU_MIPS4KC + +options BERI_LARGE_TLB Modified: stable/10/sys/mips/include/cpufunc.h ============================================================================== --- stable/10/sys/mips/include/cpufunc.h Fri Nov 1 21:15:39 2013 (r257527) +++ stable/10/sys/mips/include/cpufunc.h Fri Nov 1 21:17:45 2013 (r257528) @@ -242,8 +242,13 @@ MIPS_RW32_COP0_SEL(config3, MIPS_COP_0_C #ifdef CPU_CNMIPS MIPS_RW32_COP0_SEL(config4, MIPS_COP_0_CONFIG, 4); #endif -#ifdef CPU_NLM +#ifdef BERI_LARGE_TLB +MIPS_RW32_COP0_SEL(config5, MIPS_COP_0_CONFIG, 5); +#endif +#if defined(CPU_NLM) || defined(BERI_LARGE_TLB) MIPS_RW32_COP0_SEL(config6, MIPS_COP_0_CONFIG, 6); +#endif +#ifdef CPU_NLM MIPS_RW32_COP0_SEL(config7, MIPS_COP_0_CONFIG, 7); #endif MIPS_RW32_COP0(count, MIPS_COP_0_COUNT); Modified: stable/10/sys/mips/mips/cpu.c ============================================================================== --- stable/10/sys/mips/mips/cpu.c Fri Nov 1 21:15:39 2013 (r257527) +++ stable/10/sys/mips/mips/cpu.c Fri Nov 1 21:17:45 2013 (r257528) @@ -99,17 +99,29 @@ mips_get_identity(struct mips_cpuinfo *c /* Learn TLB size and L1 cache geometry. */ cfg1 = mips_rd_config1(); -#ifndef CPU_NLM - cpuinfo->tlb_nentries = - ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1; -#else + +#if defined(CPU_NLM) /* Account for Extended TLB entries in XLP */ tmp = mips_rd_config6(); cpuinfo->tlb_nentries = ((tmp >> 16) & 0xffff) + 1; +#elif defined(BERI_LARGE_TLB) + /* Check if we support extended TLB entries and if so activate. */ + tmp = mips_rd_config5(); +#define BERI_CP5_LTLB_SUPPORTED 0x1 + if (tmp & BERI_CP5_LTLB_SUPPORTED) { + /* See how many extra TLB entries we have. */ + tmp = mips_rd_config6(); + cpuinfo->tlb_nentries = (tmp >> 16) + 1; + /* Activate the extended entries. */ + mips_wr_config6(tmp|0x4); + } else +#endif +#if !defined(CPU_NLM) + cpuinfo->tlb_nentries = + ((cfg1 & MIPS_CONFIG1_TLBSZ_MASK) >> MIPS_CONFIG1_TLBSZ_SHIFT) + 1; #endif - - /* Add extended TLB size information from config4. */ #if defined(CPU_CNMIPS) + /* Add extended TLB size information from config4. */ cfg4 = mips_rd_config4(); if ((cfg4 & MIPS_CONFIG4_MMUEXTDEF) == MIPS_CONFIG4_MMUEXTDEF_MMUSIZEEXT) cpuinfo->tlb_nentries += (cfg4 & MIPS_CONFIG4_MMUSIZEEXT) * 0x40; @@ -124,8 +136,8 @@ mips_get_identity(struct mips_cpuinfo *c 1 << (((cfg1 & MIPS_CONFIG1_IS_MASK) >> MIPS_CONFIG1_IS_SHIFT) + 6); } -#ifndef CPU_CNMIPS /* L1 data cache. */ +#ifndef CPU_CNMIPS tmp = (cfg1 & MIPS_CONFIG1_DL_MASK) >> MIPS_CONFIG1_DL_SHIFT; if (tmp != 0) { cpuinfo->l1.dc_linesize = 1 << (tmp + 1);