From owner-svn-src-all@freebsd.org Mon Dec 4 17:02:55 2017 Return-Path: Delivered-To: svn-src-all@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 3DD8AE5DC0F; Mon, 4 Dec 2017 17:02:55 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 0AC92700BA; Mon, 4 Dec 2017 17:02:54 +0000 (UTC) (envelope-from avg@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id vB4H2seO000434; Mon, 4 Dec 2017 17:02:54 GMT (envelope-from avg@FreeBSD.org) Received: (from avg@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id vB4H2sar000433; Mon, 4 Dec 2017 17:02:54 GMT (envelope-from avg@FreeBSD.org) Message-Id: <201712041702.vB4H2sar000433@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: avg set sender to avg@FreeBSD.org using -f From: Andriy Gapon Date: Mon, 4 Dec 2017 17:02:54 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r326537 - head/sys/amd64/vmm/amd X-SVN-Group: head X-SVN-Commit-Author: avg X-SVN-Commit-Paths: head/sys/amd64/vmm/amd X-SVN-Commit-Revision: 326537 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.25 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 04 Dec 2017 17:02:55 -0000 Author: avg Date: Mon Dec 4 17:02:53 2017 New Revision: 326537 URL: https://svnweb.freebsd.org/changeset/base/326537 Log: amd-vi: clear event interrupt and overflow bits upon handling the interrupt This ensures that we can receive further event interrupts. See the description of the bits in the specification for MMIO Offset 2020h IOMMU Status Register. The bits are defined as set-by-hardware write-1-to-clear, same as all the bits in the status register. Discussed with: anish Modified: head/sys/amd64/vmm/amd/amdvi_hw.c Modified: head/sys/amd64/vmm/amd/amdvi_hw.c ============================================================================== --- head/sys/amd64/vmm/amd/amdvi_hw.c Mon Dec 4 16:47:19 2017 (r326536) +++ head/sys/amd64/vmm/amd/amdvi_hw.c Mon Dec 4 17:02:53 2017 (r326537) @@ -815,6 +815,7 @@ amdvi_event_intr(void *arg) softc->total_cmd, ctrl->cmd_tail, ctrl->cmd_head); amdvi_print_events(softc); + ctrl->status &= AMDVI_STATUS_EV_OF | AMDVI_STATUS_EV_INTR; } static void @@ -839,6 +840,7 @@ amdvi_free_evt_intr_res(device_t dev) static bool amdvi_alloc_intr_resources(struct amdvi_softc *softc) { + struct amdvi_ctrl *ctrl; device_t dev, pcib; uint64_t msi_addr; uint32_t msi_data, temp; @@ -902,6 +904,10 @@ amdvi_alloc_intr_resources(struct amdvi_softc *softc) amdvi_free_evt_intr_res(softc->dev); return (err); } + + /* Clear interrupt status bits. */ + ctrl = softc->ctrl; + ctrl->status &= AMDVI_STATUS_EV_OF | AMDVI_STATUS_EV_INTR; /* Configure MSI */ amdvi_pci_write(softc, msi_off + PCIR_MSI_ADDR, msi_addr);