From owner-svn-src-head@freebsd.org Tue Mar 24 18:16:15 2020 Return-Path: Delivered-To: svn-src-head@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id 5BFDB265097; Tue, 24 Mar 2020 18:16:15 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 48mzvy3Mkdz4GpL; Tue, 24 Mar 2020 18:16:14 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 9B98E3F2A; Tue, 24 Mar 2020 18:16:03 +0000 (UTC) (envelope-from jhb@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 02OIG37P003872; Tue, 24 Mar 2020 18:16:03 GMT (envelope-from jhb@FreeBSD.org) Received: (from jhb@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 02OIG3IO003871; Tue, 24 Mar 2020 18:16:03 GMT (envelope-from jhb@FreeBSD.org) Message-Id: <202003241816.02OIG3IO003871@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: jhb set sender to jhb@FreeBSD.org using -f From: John Baldwin Date: Tue, 24 Mar 2020 18:16:03 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r359275 - head X-SVN-Group: head X-SVN-Commit-Author: jhb X-SVN-Commit-Paths: head X-SVN-Commit-Revision: 359275 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 24 Mar 2020 18:16:15 -0000 Author: jhb Date: Tue Mar 24 18:16:02 2020 New Revision: 359275 URL: https://svnweb.freebsd.org/changeset/base/359275 Log: Disable rarely used architecture variants in make universe by default. If EXTRA_TARGETS is defined, build all supported architecture variants. By default, build architecture variants needed to provide code coverage or that are commonly used. Use this to disable building of all the hard-float and little-endian MIPS architecture variants along with n32 by default. Reviewed by: rpokala Discussed with: imp, emaste Differential Revision: https://reviews.freebsd.org/D24178 Modified: head/Makefile Modified: head/Makefile ============================================================================== --- head/Makefile Tue Mar 24 17:54:34 2020 (r359274) +++ head/Makefile Tue Mar 24 18:16:02 2020 (r359275) @@ -483,16 +483,17 @@ worlds: .PHONY .if make(universe) || make(universe_kernels) || make(tinderbox) || \ make(targets) || make(universe-toolchain) # -# Always build architectures supported by clang. Only build architectures -# only supported by GCC if a suitable toolchain is present or enabled. -# In all cases, if the user specifies TARGETS on the command line, -# honor that most of all. +# Don't build rarely used architectures unless requested. # +.if defined(EXTRA_TARGETS) +EXTRA_ARCHES_mips= mipsel mipshf mipselhf mips64el mips64hf mips64elhf +EXTRA_ARCHES_mips+= mipsn32 +.endif TARGETS?=amd64 arm arm64 i386 mips powerpc riscv _UNIVERSE_TARGETS= ${TARGETS} TARGET_ARCHES_arm?= armv6 armv7 TARGET_ARCHES_arm64?= aarch64 -TARGET_ARCHES_mips?= mipsel mips mips64el mips64 mipsn32 mipselhf mipshf mips64elhf mips64hf +TARGET_ARCHES_mips?= mips mips64 ${EXTRA_ARCHES_mips} # powerpcspe excluded until clang fixed TARGET_ARCHES_powerpc?= powerpc powerpc64 TARGET_ARCHES_riscv?= riscv64 riscv64sf