From owner-svn-src-head@freebsd.org Mon May 20 17:43:59 2019 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id BFF9815B3E89; Mon, 20 May 2019 17:43:59 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 6542189505; Mon, 20 May 2019 17:43:59 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 3FAD021996; Mon, 20 May 2019 17:43:59 +0000 (UTC) (envelope-from adrian@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id x4KHhxAq061645; Mon, 20 May 2019 17:43:59 GMT (envelope-from adrian@FreeBSD.org) Received: (from adrian@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id x4KHhxYU061644; Mon, 20 May 2019 17:43:59 GMT (envelope-from adrian@FreeBSD.org) Message-Id: <201905201743.x4KHhxYU061644@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: adrian set sender to adrian@FreeBSD.org using -f From: Adrian Chadd Date: Mon, 20 May 2019 17:43:59 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r347998 - head/sys/mips/mediatek X-SVN-Group: head X-SVN-Commit-Author: adrian X-SVN-Commit-Paths: head/sys/mips/mediatek X-SVN-Commit-Revision: 347998 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 6542189505 X-Spamd-Bar: -- Authentication-Results: mx1.freebsd.org X-Spamd-Result: default: False [-2.96 / 15.00]; local_wl_from(0.00)[FreeBSD.org]; NEURAL_HAM_MEDIUM(-1.00)[-0.999,0]; NEURAL_HAM_SHORT(-0.96)[-0.964,0]; ASN(0.00)[asn:11403, ipnet:2610:1c1:1::/48, country:US]; NEURAL_HAM_LONG(-1.00)[-1.000,0] X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 20 May 2019 17:44:00 -0000 Author: adrian Date: Mon May 20 17:43:58 2019 New Revision: 347998 URL: https://svnweb.freebsd.org/changeset/base/347998 Log: [mediatek] Add support for non-flash devices on the SPI bus of the Mediatek SoCs. The existing SPI support only worked for directly attached flash chips. it didn't implement clock programming or chipselect. It also supports transfers with unbalanced tx/rx command sizes. Submitted by: Differential Revision: https://reviews.freebsd.org/D20101 Modified: head/sys/mips/mediatek/mtk_spi_v1.c Modified: head/sys/mips/mediatek/mtk_spi_v1.c ============================================================================== --- head/sys/mips/mediatek/mtk_spi_v1.c Mon May 20 16:39:31 2019 (r347997) +++ head/sys/mips/mediatek/mtk_spi_v1.c Mon May 20 17:43:58 2019 (r347998) @@ -43,6 +43,11 @@ __FBSDID("$FreeBSD$"); #include #include +#include +#include "gpiobus_if.h" + +#include + #include #include #include "spibus_if.h" @@ -53,6 +58,7 @@ __FBSDID("$FreeBSD$"); #include #include +#include #include #include @@ -81,6 +87,8 @@ __FBSDID("$FreeBSD$"); struct mtk_spi_softc { device_t sc_dev; struct resource *sc_mem_res; + struct gpiobus_pin *gpio_cs; + int nonflash; }; static int mtk_spi_probe(device_t); @@ -127,7 +135,7 @@ mtk_spi_attach(device_t dev) sc->sc_dev = dev; rid = 0; sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, - RF_ACTIVE); + RF_SHAREABLE | RF_ACTIVE); if (!sc->sc_mem_res) { device_printf(dev, "Could not map memory\n"); return (ENXIO); @@ -138,14 +146,20 @@ mtk_spi_attach(device_t dev) return (EBUSY); } - SPI_WRITE(sc, MTK_SPICFG, MSBFIRST | SPICLKPOL | TX_ON_CLK_FALL | - SPI_CLK_DIV8); /* XXX: make it configurable */ - /* - * W25Q64CV max 104MHz, bus 120-192 MHz, so divide by 2. - * Update: divide by 4, DEV2 to fast for flash. - */ + if (ofw_bus_has_prop(dev, "non-flash")) + sc->nonflash = 1; + else + sc->nonflash = 0; - device_add_child(dev, "spibus", 0); + ofw_gpiobus_parse_gpios(dev, "cs-gpios", &sc->gpio_cs); + + if (sc->gpio_cs != NULL) { + GPIO_PIN_SETFLAGS(sc->gpio_cs->dev, sc->gpio_cs->pin, + GPIO_PIN_OUTPUT); + GPIO_PIN_SET(sc->gpio_cs->dev, sc->gpio_cs->pin, 1); + } + + device_add_child(dev, "spibus", -1); return (bus_generic_attach(dev)); } @@ -169,7 +183,12 @@ mtk_spi_chip_activate(struct mtk_spi_softc *sc) /* * Put all CSx to low */ - SPI_CLEAR_BITS(sc, MTK_SPICTL, CS_HIGH | HIZSMOSI); + if (sc->gpio_cs != NULL) { + GPIO_PIN_SET(sc->gpio_cs->dev, sc->gpio_cs->pin, 0); + SPI_CLEAR_BITS(sc, MTK_SPICTL, HIZSMOSI); + } else { + SPI_CLEAR_BITS(sc, MTK_SPICTL, CS_HIGH | HIZSMOSI); + } } static void @@ -179,7 +198,12 @@ mtk_spi_chip_deactivate(struct mtk_spi_softc *sc) /* * Put all CSx to high */ - SPI_SET_BITS(sc, MTK_SPICTL, CS_HIGH | HIZSMOSI); + if (sc->gpio_cs != NULL) { + GPIO_PIN_SET(sc->gpio_cs->dev, sc->gpio_cs->pin, 1); + SPI_SET_BITS(sc, MTK_SPICTL, HIZSMOSI); + } else { + SPI_SET_BITS(sc, MTK_SPICTL, CS_HIGH | HIZSMOSI); + } } static int @@ -224,12 +248,15 @@ mtk_spi_transfer(device_t dev, device_t child, struct { struct mtk_spi_softc *sc; uint8_t *buf, byte, *tx_buf; - uint32_t cs; + uint32_t cs, clock, mode; int i, sz, error = 0, write = 0; + int div, clk, cfgreg; sc = device_get_softc(dev); spibus_get_cs(child, &cs); + spibus_get_clock(child, &clock); + spibus_get_mode(child, &mode); cs &= ~SPIBUS_CS_HIGH; @@ -237,44 +264,80 @@ mtk_spi_transfer(device_t dev, device_t child, struct /* Only 1 CS */ return (ENXIO); - /* There is always a command to transfer. */ - tx_buf = (uint8_t *)(cmd->tx_cmd); - - /* Perform some fixup because MTK dont support duplex SPI */ - switch(tx_buf[0]) { - case CMD_READ_IDENT: - cmd->tx_cmd_sz = 1; - cmd->rx_cmd_sz = 3; + cfgreg = MSBFIRST; + switch(mode) { + case 0: /* This is workadound because of + mode 0 not work this soc. */ + case 3: + cfgreg |= SPICLKPOL | TX_ON_CLK_FALL; break; - case CMD_ENTER_4B_MODE: - case CMD_EXIT_4B_MODE: - case CMD_WRITE_ENABLE: - case CMD_WRITE_DISABLE: - cmd->tx_cmd_sz = 1; - cmd->rx_cmd_sz = 0; + case 1: + cfgreg |= TX_ON_CLK_FALL; break; - case CMD_READ_STATUS: - cmd->tx_cmd_sz = 1; - cmd->rx_cmd_sz = 1; + case 2: + cfgreg |= CAPT_ON_CLK_FALL; break; - case CMD_READ: - case CMD_FAST_READ: - cmd->rx_cmd_sz = cmd->tx_data_sz = 0; - break; - case CMD_SECTOR_ERASE: - cmd->rx_cmd_sz = 0; - break; - case CMD_PAGE_PROGRAM: - cmd->rx_cmd_sz = cmd->rx_data_sz = 0; - break; - } + } + + /* + * W25Q64CV max 104MHz, bus 120-192 MHz, so divide by 2. + * Update: divide by 4, DEV2 to fast for flash. + */ + if (clock != 0) { + div = (mtk_soc_get_cpuclk() + (clock - 1)) / clock; + clk = fls(div) - 2; + if (clk < 0) + clk = 0; + else if (clk > 6) + clk = 6; + } else { + clk = 6; + } + + SPI_WRITE(sc, MTK_SPICFG, cfgreg | clk); + + if (sc->nonflash == 0) { + /* There is always a command to transfer. */ + tx_buf = (uint8_t *)(cmd->tx_cmd); + + /* Perform some fixup because MTK dont support duplex SPI */ + switch(tx_buf[0]) { + case CMD_READ_IDENT: + cmd->tx_cmd_sz = 1; + cmd->rx_cmd_sz = 3; + break; + case CMD_ENTER_4B_MODE: + case CMD_EXIT_4B_MODE: + case CMD_WRITE_ENABLE: + case CMD_WRITE_DISABLE: + cmd->tx_cmd_sz = 1; + cmd->rx_cmd_sz = 0; + break; + case CMD_READ_STATUS: + cmd->tx_cmd_sz = 1; + cmd->rx_cmd_sz = 1; + break; + case CMD_READ: + case CMD_FAST_READ: + cmd->rx_cmd_sz = cmd->tx_data_sz = 0; + break; + case CMD_SECTOR_ERASE: + cmd->rx_cmd_sz = 0; + break; + case CMD_PAGE_PROGRAM: + cmd->rx_cmd_sz = cmd->rx_data_sz = 0; + break; + } + } mtk_spi_chip_activate(sc); if (cmd->tx_cmd_sz + cmd->rx_cmd_sz) { buf = (uint8_t *)(cmd->rx_cmd); tx_buf = (uint8_t *)(cmd->tx_cmd); - sz = cmd->tx_cmd_sz + cmd->rx_cmd_sz; + sz = cmd->tx_cmd_sz; + if (sc->nonflash == 0) + sz += cmd->rx_cmd_sz; for (i = 0; i < sz; i++) { if(i < cmd->tx_cmd_sz) {