From owner-freebsd-ppc@FreeBSD.ORG Thu Apr 3 00:23:55 2008 Return-Path: Delivered-To: freebsd-ppc@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 656291065670 for ; Thu, 3 Apr 2008 00:23:55 +0000 (UTC) (envelope-from xcllnt@mac.com) Received: from smtpoutm.mac.com (smtpoutm.mac.com [17.148.16.79]) by mx1.freebsd.org (Postfix) with ESMTP id 4DBD48FC1C for ; Thu, 3 Apr 2008 00:23:55 +0000 (UTC) (envelope-from xcllnt@mac.com) Received: from mac.com (asmtp001-s [10.150.69.64]) by smtpoutm.mac.com (Xserve/smtpout016/MantshX 4.0) with ESMTP id m330NsfT008793; Wed, 2 Apr 2008 17:23:55 -0700 (PDT) Received: from [192.168.1.100] (209-128-86-226.bayarea.net [209.128.86.226]) (authenticated bits=0) by mac.com (Xserve/asmtp001/MantshX 4.0) with ESMTP id m330NrOQ006386 (version=TLSv1/SSLv3 cipher=AES128-SHA bits=128 verify=NO); Wed, 2 Apr 2008 17:23:53 -0700 (PDT) Message-Id: From: Marcel Moolenaar To: Nathan Whitehorn In-Reply-To: <47F422A0.9080907@uchicago.edu> Content-Type: text/plain; charset=US-ASCII; format=flowed; delsp=yes Content-Transfer-Encoding: 7bit Mime-Version: 1.0 (Apple Message framework v919.2) Date: Wed, 2 Apr 2008 17:23:51 -0700 References: <47E06B23.7060400@uchicago.edu> <20080325023040.ab0daa19.stas@FreeBSD.org> <47E8527B.2050002@uchicago.edu> <47F39EF4.8040800@uchicago.edu> <47F3D2BC.7060001@uchicago.edu> <47F422A0.9080907@uchicago.edu> X-Mailer: Apple Mail (2.919.2) Cc: freebsd-ppc@freebsd.org Subject: Re: BMAC Ethernet Driver X-BeenThere: freebsd-ppc@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the PowerPC List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 03 Apr 2008 00:23:55 -0000 On Apr 2, 2008, at 5:19 PM, Nathan Whitehorn wrote: >>> From what you say it seems that the driver is commitable at >>> this time. I can't test it, but I can definitely commit. >>> Just let me know... >> I would like some tests with one of the other two revisions of the >> chip, of course, but any fixes should be minor. The real concern, >> on my part, for committing it is whether the macio IRQ patch breaks >> anything. If you have both an interrupts property and an >> AAPL,interrupts in OF, with multiple interrupts listed, it will >> cause all of the AAPL,interrupts IRQ resources to be renumbered. >> >> At the moment, we only support two devices (SCC and macio ATA) >> hanging off macio, so the set of things to be checked is limited. I >> know that the ATA code still works, but I suspect it might break >> the scc UART support, since it has several interrupts. So if you >> have any mac hardware at all with an SCC part you can test, it >> might be good to check that before committing. > > As it turns out, this description is not quite accurate -- it will > break devices with children with more than one interrupt. This > description fits SCC, where each child has three interrupts (one for > general stuff, and two for the DBDMA channels). Thus SCC channel B > is likely to stop working without some fixups to its interrupt > allocation on macio. I'll test the patch... -- Marcel Moolenaar xcllnt@mac.com