From owner-p4-projects@FreeBSD.ORG Sun Nov 2 15:05:50 2003 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id C44D816A4D1; Sun, 2 Nov 2003 15:05:49 -0800 (PST) Delivered-To: perforce@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id 9DD9116A4CE for ; Sun, 2 Nov 2003 15:05:49 -0800 (PST) Received: from repoman.freebsd.org (repoman.freebsd.org [216.136.204.115]) by mx1.FreeBSD.org (Postfix) with ESMTP id 761D543FD7 for ; Sun, 2 Nov 2003 15:05:48 -0800 (PST) (envelope-from jmallett@freebsd.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.12.9/8.12.9) with ESMTP id hA2N5mXJ042517 for ; Sun, 2 Nov 2003 15:05:48 -0800 (PST) (envelope-from jmallett@freebsd.org) Received: (from perforce@localhost) by repoman.freebsd.org (8.12.9/8.12.9/Submit) id hA2N5lUm042514 for perforce@freebsd.org; Sun, 2 Nov 2003 15:05:47 -0800 (PST) (envelope-from jmallett@freebsd.org) Date: Sun, 2 Nov 2003 15:05:47 -0800 (PST) Message-Id: <200311022305.hA2N5lUm042514@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to jmallett@freebsd.org using -f From: Juli Mallett To: Perforce Change Reviews Subject: PERFORCE change 41142 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 02 Nov 2003 23:05:50 -0000 http://perforce.freebsd.org/chv.cgi?CH=41142 Change 41142 by jmallett@jmallett_dalek on 2003/11/02 15:04:49 If we run across a 32-bit TLB refill, then we're confused, but better to go right into trap than to call panic. Affected files ... .. //depot/projects/mips/sys/mips/mips/exception.S#6 edit Differences ... ==== //depot/projects/mips/sys/mips/mips/exception.S#6 (text+ko) ==== @@ -141,15 +141,27 @@ LEAF(TLBMissVector) .set noat - dla a0, 1f - dla k0, panic - dmtc0 k0, MIPS_COP_0_EXC_PC + dsubu sp, sp, TF_SIZE + dla k0, 1f + j exception_save_registers + move k1, sp +1: + /* + * No turning back, and nothing we can do. Just call into + * trap and let it tell the user lovely things about how bad + * their cache has been, + */ + mfc0 a1, MIPS_COP_0_CAUSE + dmfc0 a2, MIPS_COP_0_BAD_VADDR + jal trap + move a0, k1 + + jal exception_restore_registers + move a0, sp + daddu sp, sp, TF_SIZE eret .set at VEND(TLBMissVector) - .data -1: .asciiz "32-bit TLB miss!?\n" - .text /* * XXX kernel only. For now that makes sense.