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Date:      Sat, 3 Sep 2011 08:03:25 +0000 (UTC)
From:      "Jayachandran C." <jchandra@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-user@freebsd.org
Subject:   svn commit: r225363 - in user/jchandra/mips-xlp-support/sys/mips: conf nlm nlm/hal
Message-ID:  <201109030803.p8383Pbr036048@svn.freebsd.org>

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Author: jchandra
Date: Sat Sep  3 08:03:25 2011
New Revision: 225363
URL: http://svn.freebsd.org/changeset/base/225363

Log:
  HAL updates
  
  Update hardware access register defs and functions to be more in sync
  with other platforms

Deleted:
  user/jchandra/mips-xlp-support/sys/mips/nlm/hal/cop0.h
Modified:
  user/jchandra/mips-xlp-support/sys/mips/conf/XLP64
  user/jchandra/mips-xlp-support/sys/mips/nlm/cms.c
  user/jchandra/mips-xlp-support/sys/mips/nlm/hal/bridge.h
  user/jchandra/mips-xlp-support/sys/mips/nlm/hal/cop2.h
  user/jchandra/mips-xlp-support/sys/mips/nlm/hal/cpucontrol.h
  user/jchandra/mips-xlp-support/sys/mips/nlm/hal/fmn.c
  user/jchandra/mips-xlp-support/sys/mips/nlm/hal/fmn.h
  user/jchandra/mips-xlp-support/sys/mips/nlm/hal/iomap.h
  user/jchandra/mips-xlp-support/sys/mips/nlm/hal/mips-extns.h
  user/jchandra/mips-xlp-support/sys/mips/nlm/hal/mmio.h
  user/jchandra/mips-xlp-support/sys/mips/nlm/hal/mmu.h
  user/jchandra/mips-xlp-support/sys/mips/nlm/hal/pcibus.h
  user/jchandra/mips-xlp-support/sys/mips/nlm/hal/pic.h
  user/jchandra/mips-xlp-support/sys/mips/nlm/hal/sys.h
  user/jchandra/mips-xlp-support/sys/mips/nlm/hal/uart.h
  user/jchandra/mips-xlp-support/sys/mips/nlm/hal/usb.h
  user/jchandra/mips-xlp-support/sys/mips/nlm/intr_machdep.c
  user/jchandra/mips-xlp-support/sys/mips/nlm/mpreset.S
  user/jchandra/mips-xlp-support/sys/mips/nlm/uart_bus_xlp_iodi.c
  user/jchandra/mips-xlp-support/sys/mips/nlm/uart_cpu_xlp.c
  user/jchandra/mips-xlp-support/sys/mips/nlm/uart_pci_xlp.c
  user/jchandra/mips-xlp-support/sys/mips/nlm/usb_init.c
  user/jchandra/mips-xlp-support/sys/mips/nlm/xlp.h
  user/jchandra/mips-xlp-support/sys/mips/nlm/xlp_machdep.c
  user/jchandra/mips-xlp-support/sys/mips/nlm/xlp_pci.c

Modified: user/jchandra/mips-xlp-support/sys/mips/conf/XLP64
==============================================================================
--- user/jchandra/mips-xlp-support/sys/mips/conf/XLP64	Sat Sep  3 07:15:14 2011	(r225362)
+++ user/jchandra/mips-xlp-support/sys/mips/conf/XLP64	Sat Sep  3 08:03:25 2011	(r225363)
@@ -77,7 +77,6 @@ options 	ALT_BREAK_TO_DEBUGGER
 #options 	KTR			# ktr(4) and ktrdump(8) support
 #options 	KTR_COMPILE=(KTR_LOCK|KTR_PROC|KTR_INTR|KTR_CALLOUT|KTR_UMA|KTR_SYSC)
 #options 	KTR_ENTRIES=131072
-#options 	LOCK_DEBUG
 #options 	LOCK_PROFILING
 
 
@@ -100,6 +99,6 @@ device		msk
 device		da
 device		scbus
 
-device		usb
-device		ehci
-device		umass
+#device		usb
+#device		ehci
+#device		umass

Modified: user/jchandra/mips-xlp-support/sys/mips/nlm/cms.c
==============================================================================
--- user/jchandra/mips-xlp-support/sys/mips/nlm/cms.c	Sat Sep  3 07:15:14 2011	(r225362)
+++ user/jchandra/mips-xlp-support/sys/mips/nlm/cms.c	Sat Sep  3 08:03:25 2011	(r225363)
@@ -58,7 +58,7 @@ __FBSDID("$FreeBSD: head/sys/mips/rmi/fm
 #include <mips/nlm/hal/mips-extns.h>
 #include <mips/nlm/hal/mmio.h>
 #include <mips/nlm/hal/iomap.h>
-#include <mips/nlm/hal/cop0.h>
+#include <mips/nlm/hal/cpuinfo.h>
 #include <mips/nlm/hal/cop2.h>
 #include <mips/nlm/hal/fmn.h>
 #include <mips/nlm/hal/pic.h>
@@ -108,7 +108,7 @@ xlp_msgring_config(void)
 	int i;
 
 	/* TODO: Add other nodes */
-	xlp_cms_base = nlm_regbase_cms(0);
+	xlp_cms_base = nlm_get_cms_regbase(0);
 
 	mtx_init(&msgmap_lock, "msgring", NULL, MTX_SPIN);
 	if (xlp_threads_per_core < xlp_msg_threads_per_core)
@@ -210,7 +210,7 @@ xlp_msgring_cpu_init(uint32_t cpuid)
 {
 	int queue,i;
 
-	queue = XLP_CMS_CPU_PUSHQ(0, ((cpuid >> 2) & 0x7), (cpuid & 0x3), 0);
+	queue = CMS_CPU_PUSHQ(0, ((cpuid >> 2) & 0x7), (cpuid & 0x3), 0);
 	/* temp allocate 4 segments to each output queue */
 	nlm_cms_alloc_onchip_q(xlp_cms_base, queue, 4);
 	/* Enable high watermark and non empty interrupt */

Modified: user/jchandra/mips-xlp-support/sys/mips/nlm/hal/bridge.h
==============================================================================
--- user/jchandra/mips-xlp-support/sys/mips/nlm/hal/bridge.h	Sat Sep  3 07:15:14 2011	(r225362)
+++ user/jchandra/mips-xlp-support/sys/mips/nlm/hal/bridge.h	Sat Sep  3 08:03:25 2011	(r225363)
@@ -27,8 +27,8 @@
  *
  * NETLOGIC_BSD */
 
-#ifndef __NLM_BRIDGE_H__
-#define __NLM_BRIDGE_H__
+#ifndef __NLM_HAL_BRIDGE_H__
+#define __NLM_HAL_BRIDGE_H__
 
 /**
 * @file_name mio.h
@@ -36,141 +36,147 @@
 * @brief Basic definitions of XLP memory and io subsystem
 */
 
-/* BRIDGE specific registers */
-#define XLP_BRIDGE_MODE_REG			0x40
-#define XLP_BRIDGE_PCI_CFG_BASE_REG		0x41
-#define XLP_BRIDGE_PCI_CFG_LIMIT_REG		0x42
-#define XLP_BRIDGE_PCIE_CFG_BASE_REG		0x43
-#define XLP_BRIDGE_PCIE_CFG_LIMIT_REG		0x44
-#define XLP_BRIDGE_BUSNUM_BAR0_REG		0x45
-#define XLP_BRIDGE_BUSNUM_BAR1_REG		0x46
-#define XLP_BRIDGE_BUSNUM_BAR2_REG		0x47
-#define XLP_BRIDGE_BUSNUM_BAR3_REG		0x48
-#define XLP_BRIDGE_BUSNUM_BAR4_REG		0x49
-#define XLP_BRIDGE_BUSNUM_BAR5_REG		0x4a
-#define XLP_BRIDGE_BUSNUM_BAR6_REG		0x4b
-#define XLP_BRIDGE_FLASH_BAR0_REG		0x4c
-#define XLP_BRIDGE_FLASH_BAR1_REG		0x4d
-#define XLP_BRIDGE_FLASH_BAR2_REG		0x4e
-#define XLP_BRIDGE_FLASH_BAR3_REG		0x4f
-#define XLP_BRIDGE_FLASH_LIMIT0_REG		0x50
-#define XLP_BRIDGE_FLASH_LIMIT1_REG		0x51
-#define XLP_BRIDGE_FLASH_LIMIT2_REG		0x52
-#define XLP_BRIDGE_FLASH_LIMIT3_REG		0x53
-
-#define XLP_BRIDGE_DRAM_BAR_REG(i)		(0x54 + (i))
-#define XLP_BRIDGE_DRAM_BAR0_REG		0x54
-#define XLP_BRIDGE_DRAM_BAR1_REG		0x55
-#define XLP_BRIDGE_DRAM_BAR2_REG		0x56
-#define XLP_BRIDGE_DRAM_BAR3_REG		0x57
-#define XLP_BRIDGE_DRAM_BAR4_REG		0x58
-#define XLP_BRIDGE_DRAM_BAR5_REG		0x59
-#define XLP_BRIDGE_DRAM_BAR6_REG		0x5a
-#define XLP_BRIDGE_DRAM_BAR7_REG		0x5b
-
-#define XLP_BRIDGE_DRAM_LIMIT_REG(i)		(0x5c + (i))
-#define XLP_BRIDGE_DRAM_LIMIT0_REG		0x5c
-#define XLP_BRIDGE_DRAM_LIMIT1_REG		0x5d
-#define XLP_BRIDGE_DRAM_LIMIT2_REG		0x5e
-#define XLP_BRIDGE_DRAM_LIMIT3_REG		0x5f
-#define XLP_BRIDGE_DRAM_LIMIT4_REG		0x60
-#define XLP_BRIDGE_DRAM_LIMIT5_REG		0x61
-#define XLP_BRIDGE_DRAM_LIMIT6_REG		0x62
-#define XLP_BRIDGE_DRAM_LIMIT7_REG		0x63
-
-#define XLP_BRIDGE_DRAM_NODE_TRANSLN0_REG	0x64
-#define XLP_BRIDGE_DRAM_NODE_TRANSLN1_REG	0x65
-#define XLP_BRIDGE_DRAM_NODE_TRANSLN2_REG	0x66
-#define XLP_BRIDGE_DRAM_NODE_TRANSLN3_REG	0x67
-#define XLP_BRIDGE_DRAM_NODE_TRANSLN4_REG	0x68
-#define XLP_BRIDGE_DRAM_NODE_TRANSLN5_REG	0x69
-#define XLP_BRIDGE_DRAM_NODE_TRANSLN6_REG	0x6a
-#define XLP_BRIDGE_DRAM_NODE_TRANSLN7_REG	0x6b
-#define XLP_BRIDGE_DRAM_CHNL_TRANSLN0_REG	0x6c
-#define XLP_BRIDGE_DRAM_CHNL_TRANSLN1_REG	0x6d
-#define XLP_BRIDGE_DRAM_CHNL_TRANSLN2_REG	0x6e
-#define XLP_BRIDGE_DRAM_CHNL_TRANSLN3_REG	0x6f
-#define XLP_BRIDGE_DRAM_CHNL_TRANSLN4_REG	0x70
-#define XLP_BRIDGE_DRAM_CHNL_TRANSLN5_REG	0x71
-#define XLP_BRIDGE_DRAM_CHNL_TRANSLN6_REG	0x72
-#define XLP_BRIDGE_DRAM_CHNL_TRANSLN7_REG	0x73
-#define XLP_BRIDGE_PCIEMEM_BASE0_REG		0x74
-#define XLP_BRIDGE_PCIEMEM_BASE1_REG		0x75
-#define XLP_BRIDGE_PCIEMEM_BASE2_REG		0x76
-#define XLP_BRIDGE_PCIEMEM_BASE3_REG		0x77
-#define XLP_BRIDGE_PCIEMEM_LIMIT0_REG		0x78
-#define XLP_BRIDGE_PCIEMEM_LIMIT1_REG		0x79
-#define XLP_BRIDGE_PCIEMEM_LIMIT2_REG		0x7a
-#define XLP_BRIDGE_PCIEMEM_LIMIT3_REG		0x7b
-#define XLP_BRIDGE_PCIEIO_BASE0_REG		0x7c
-#define XLP_BRIDGE_PCIEIO_BASE1_REG		0x7d
-#define XLP_BRIDGE_PCIEIO_BASE2_REG		0x7e
-#define XLP_BRIDGE_PCIEIO_BASE3_REG		0x7f
-#define XLP_BRIDGE_PCIEIO_LIMIT0_REG		0x80
-#define XLP_BRIDGE_PCIEIO_LIMIT1_REG		0x81
-#define XLP_BRIDGE_PCIEIO_LIMIT2_REG		0x82
-#define XLP_BRIDGE_PCIEIO_LIMIT3_REG		0x83
-#define XLP_BRIDGE_PCIEMEM_BASE4_REG		0x84
-#define XLP_BRIDGE_PCIEMEM_BASE5_REG		0x85
-#define XLP_BRIDGE_PCIEMEM_BASE6_REG		0x86
-#define XLP_BRIDGE_PCIEMEM_LIMIT4_REG		0x87
-#define XLP_BRIDGE_PCIEMEM_LIMIT5_REG		0x88
-#define XLP_BRIDGE_PCIEMEM_LIMIT6_REG		0x89
-#define XLP_BRIDGE_PCIEIO_BASE4_REG		0x8a
-#define XLP_BRIDGE_PCIEIO_BASE5_REG		0x8b
-#define XLP_BRIDGE_PCIEIO_BASE6_REG		0x8c
-#define XLP_BRIDGE_PCIEIO_LIMIT4_REG		0x8d
-#define XLP_BRIDGE_PCIEIO_LIMIT5_REG		0x8e
-#define XLP_BRIDGE_PCIEIO_LIMIT6_REG		0x8f
-#define XLP_BRIDGE_NBU_EVENT_CNT_CTL_REG	0x90
-#define XLP_BRIDGE_EVNTCTR1_LOW_REG		0x91
-#define XLP_BRIDGE_EVNTCTR1_HI_REG		0x92
-#define XLP_BRIDGE_EVNT_CNT_CTL2_REG		0x93
-#define XLP_BRIDGE_EVNTCTR2_LOW_REG		0x94
-#define XLP_BRIDGE_EVNTCTR2_HI_REG		0x95
-#define XLP_BRIDGE_TRACEBUF_MATCH_REG0		0x96
-#define XLP_BRIDGE_TRACEBUF_MATCH_REG1		0x97
-#define XLP_BRIDGE_TRACEBUF_MATCH_LOW_REG	0x98
-#define XLP_BRIDGE_TRACEBUF_MATCH_HI_REG	0x99
-#define XLP_BRIDGE_TRACEBUF_CTRL_REG		0x9a
-#define XLP_BRIDGE_TRACEBUF_INIT_REG		0x9b
-#define XLP_BRIDGE_TRACEBUF_ACCESS_REG		0x9c
-#define XLP_BRIDGE_TRACEBUF_READ_DATA_REG0	0x9d
-#define XLP_BRIDGE_TRACEBUF_READ_DATA_REG1	0x9d
-#define XLP_BRIDGE_TRACEBUF_READ_DATA_REG2	0x9f
-#define XLP_BRIDGE_TRACEBUF_READ_DATA_REG3	0xa0
-#define XLP_BRIDGE_TRACEBUF_STATUS_REG		0xa1
-#define XLP_BRIDGE_ADDRESS_ERROR0_REG		0xa2
-#define XLP_BRIDGE_ADDRESS_ERROR1_REG		0xa3
-#define XLP_BRIDGE_ADDRESS_ERROR2_REG		0xa4
-#define XLP_BRIDGE_TAG_ECC_ADDR_ERROR0_REG	0xa5
-#define XLP_BRIDGE_TAG_ECC_ADDR_ERROR1_REG	0xa6
-#define XLP_BRIDGE_TAG_ECC_ADDR_ERROR2_REG	0xa7
-#define XLP_BRIDGE_LINE_FLUSH_REG0		0xa8
-#define XLP_BRIDGE_LINE_FLUSH_REG1		0xa9
-#define XLP_BRIDGE_NODE_ID_REG			0xaa
-#define XLP_BRIDGE_ERROR_INTERRUPT_EN_REG	0xab
-#define XLP_BRIDGE_PCIE0_WEIGHT_REG		0x300
-#define XLP_BRIDGE_PCIE1_WEIGHT_REG		0x301
-#define XLP_BRIDGE_PCIE2_WEIGHT_REG		0x302
-#define XLP_BRIDGE_PCIE3_WEIGHT_REG		0x303
-#define XLP_BRIDGE_USB_WEIGHT_REG		0x304
-#define XLP_BRIDGE_NET_WEIGHT_REG		0x305
-#define XLP_BRIDGE_POE_WEIGHT_REG		0x306
-#define XLP_BRIDGE_CMS_WEIGHT_REG		0x307
-#define XLP_BRIDGE_DMAENG_WEIGHT_REG		0x308
-#define XLP_BRIDGE_SEC_WEIGHT_REG		0x309
-#define XLP_BRIDGE_COMP_WEIGHT_REG		0x30a
-#define XLP_BRIDGE_GIO_WEIGHT_REG		0x30b
-#define XLP_BRIDGE_FLASH_WEIGHT_REG		0x30c
+/*
+ * BRIDGE specific registers
+ *
+ * These registers start after the PCIe header, which has 0x40
+ * standard entries
+ */
+#define BRIDGE_MODE			0x00
+#define BRIDGE_PCI_CFG_BASE		0x01
+#define BRIDGE_PCI_CFG_LIMIT		0x02
+#define BRIDGE_PCIE_CFG_BASE		0x03
+#define BRIDGE_PCIE_CFG_LIMIT		0x04
+#define BRIDGE_BUSNUM_BAR0		0x05
+#define BRIDGE_BUSNUM_BAR1		0x06
+#define BRIDGE_BUSNUM_BAR2		0x07
+#define BRIDGE_BUSNUM_BAR3		0x08
+#define BRIDGE_BUSNUM_BAR4		0x09
+#define BRIDGE_BUSNUM_BAR5		0x0a
+#define BRIDGE_BUSNUM_BAR6		0x0b
+#define BRIDGE_FLASH_BAR0		0x0c
+#define BRIDGE_FLASH_BAR1		0x0d
+#define BRIDGE_FLASH_BAR2		0x0e
+#define BRIDGE_FLASH_BAR3		0x0f
+#define BRIDGE_FLASH_LIMIT0		0x10
+#define BRIDGE_FLASH_LIMIT1		0x11
+#define BRIDGE_FLASH_LIMIT2		0x12
+#define BRIDGE_FLASH_LIMIT3		0x13
+
+#define BRIDGE_DRAM_BAR(i)		(0x14 + (i))
+#define BRIDGE_DRAM_BAR0		0x14
+#define BRIDGE_DRAM_BAR1		0x15
+#define BRIDGE_DRAM_BAR2		0x16
+#define BRIDGE_DRAM_BAR3		0x17
+#define BRIDGE_DRAM_BAR4		0x18
+#define BRIDGE_DRAM_BAR5		0x19
+#define BRIDGE_DRAM_BAR6		0x1a
+#define BRIDGE_DRAM_BAR7		0x1b
+
+#define BRIDGE_DRAM_LIMIT(i)		(0x1c + (i))
+#define BRIDGE_DRAM_LIMIT0		0x1c
+#define BRIDGE_DRAM_LIMIT1		0x1d
+#define BRIDGE_DRAM_LIMIT2		0x1e
+#define BRIDGE_DRAM_LIMIT3		0x1f
+#define BRIDGE_DRAM_LIMIT4		0x20
+#define BRIDGE_DRAM_LIMIT5		0x21
+#define BRIDGE_DRAM_LIMIT6		0x22
+#define BRIDGE_DRAM_LIMIT7		0x23
+
+#define BRIDGE_DRAM_NODE_TRANSLN0	0x24
+#define BRIDGE_DRAM_NODE_TRANSLN1	0x25
+#define BRIDGE_DRAM_NODE_TRANSLN2	0x26
+#define BRIDGE_DRAM_NODE_TRANSLN3	0x27
+#define BRIDGE_DRAM_NODE_TRANSLN4	0x28
+#define BRIDGE_DRAM_NODE_TRANSLN5	0x29
+#define BRIDGE_DRAM_NODE_TRANSLN6	0x2a
+#define BRIDGE_DRAM_NODE_TRANSLN7	0x2b
+#define BRIDGE_DRAM_CHNL_TRANSLN0	0x2c
+#define BRIDGE_DRAM_CHNL_TRANSLN1	0x2d
+#define BRIDGE_DRAM_CHNL_TRANSLN2	0x2e
+#define BRIDGE_DRAM_CHNL_TRANSLN3	0x2f
+#define BRIDGE_DRAM_CHNL_TRANSLN4	0x30
+#define BRIDGE_DRAM_CHNL_TRANSLN5	0x31
+#define BRIDGE_DRAM_CHNL_TRANSLN6	0x32
+#define BRIDGE_DRAM_CHNL_TRANSLN7	0x33
+#define BRIDGE_PCIEMEM_BASE0		0x34
+#define BRIDGE_PCIEMEM_BASE1		0x35
+#define BRIDGE_PCIEMEM_BASE2		0x36
+#define BRIDGE_PCIEMEM_BASE3		0x37
+#define BRIDGE_PCIEMEM_LIMIT0		0x38
+#define BRIDGE_PCIEMEM_LIMIT1		0x39
+#define BRIDGE_PCIEMEM_LIMIT2		0x3a
+#define BRIDGE_PCIEMEM_LIMIT3		0x3b
+#define BRIDGE_PCIEIO_BASE0		0x3c
+#define BRIDGE_PCIEIO_BASE1		0x3d
+#define BRIDGE_PCIEIO_BASE2		0x3e
+#define BRIDGE_PCIEIO_BASE3		0x3f
+#define BRIDGE_PCIEIO_LIMIT0		0x40
+#define BRIDGE_PCIEIO_LIMIT1		0x41
+#define BRIDGE_PCIEIO_LIMIT2		0x42
+#define BRIDGE_PCIEIO_LIMIT3		0x43
+#define BRIDGE_PCIEMEM_BASE4		0x44
+#define BRIDGE_PCIEMEM_BASE5		0x45
+#define BRIDGE_PCIEMEM_BASE6		0x46
+#define BRIDGE_PCIEMEM_LIMIT4		0x47
+#define BRIDGE_PCIEMEM_LIMIT5		0x48
+#define BRIDGE_PCIEMEM_LIMIT6		0x49
+#define BRIDGE_PCIEIO_BASE4		0x4a
+#define BRIDGE_PCIEIO_BASE5		0x4b
+#define BRIDGE_PCIEIO_BASE6		0x4c
+#define BRIDGE_PCIEIO_LIMIT4		0x4d
+#define BRIDGE_PCIEIO_LIMIT5		0x4e
+#define BRIDGE_PCIEIO_LIMIT6		0x4f
+#define BRIDGE_NBU_EVENT_CNT_CTL	0x50
+#define BRIDGE_EVNTCTR1_LOW		0x51
+#define BRIDGE_EVNTCTR1_HI		0x52
+#define BRIDGE_EVNT_CNT_CTL2		0x53
+#define BRIDGE_EVNTCTR2_LOW		0x54
+#define BRIDGE_EVNTCTR2_HI		0x55
+#define BRIDGE_TRACEBUF_MATCH0		0x56
+#define BRIDGE_TRACEBUF_MATCH1		0x57
+#define BRIDGE_TRACEBUF_MATCH_LOW	0x58
+#define BRIDGE_TRACEBUF_MATCH_HI	0x59
+#define BRIDGE_TRACEBUF_CTRL		0x5a
+#define BRIDGE_TRACEBUF_INIT		0x5b
+#define BRIDGE_TRACEBUF_ACCESS		0x5c
+#define BRIDGE_TRACEBUF_READ_DATA0	0x5d
+#define BRIDGE_TRACEBUF_READ_DATA1	0x5d
+#define BRIDGE_TRACEBUF_READ_DATA2	0x5f
+#define BRIDGE_TRACEBUF_READ_DATA3	0x60
+#define BRIDGE_TRACEBUF_STATUS		0x61
+#define BRIDGE_ADDRESS_ERROR0		0x62
+#define BRIDGE_ADDRESS_ERROR1		0x63
+#define BRIDGE_ADDRESS_ERROR2		0x64
+#define BRIDGE_TAG_ECC_ADDR_ERROR0	0x65
+#define BRIDGE_TAG_ECC_ADDR_ERROR1	0x66
+#define BRIDGE_TAG_ECC_ADDR_ERROR2	0x67
+#define BRIDGE_LINE_FLUSH0		0x68
+#define BRIDGE_LINE_FLUSH1		0x69
+#define BRIDGE_NODE_ID			0x6a
+#define BRIDGE_ERROR_INTERRUPT_EN	0x6b
+#define BRIDGE_PCIE0_WEIGHT		0x2c0
+#define BRIDGE_PCIE1_WEIGHT		0x2c1
+#define BRIDGE_PCIE2_WEIGHT		0x2c2
+#define BRIDGE_PCIE3_WEIGHT		0x2c3
+#define BRIDGE_USB_WEIGHT		0x2c4
+#define BRIDGE_NET_WEIGHT		0x2c5
+#define BRIDGE_POE_WEIGHT		0x2c6
+#define BRIDGE_CMS_WEIGHT		0x2c7
+#define BRIDGE_DMAENG_WEIGHT		0x2c8
+#define BRIDGE_SEC_WEIGHT		0x2c9
+#define BRIDGE_COMP_WEIGHT		0x2ca
+#define BRIDGE_GIO_WEIGHT		0x2cb
+#define BRIDGE_FLASH_WEIGHT		0x2cc
 
 #if !defined(LOCORE) && !defined(__ASSEMBLY__)
 
-#define nlm_rdreg_bridge(b, r)		nlm_read_reg_kseg(b, r)
-#define nlm_wreg_bridge(b, r, v)	nlm_write_reg_kseg(b, r, v)
-#define	nlm_pcibase_bridge(node)	nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))
-#define	nlm_regbase_bridge(node)	nlm_pcibase_bridge(node)
+#define nlm_read_bridge_reg(b, r)	nlm_read_reg(b, r)
+#define nlm_write_bridge_reg(b, r, v)	nlm_write_reg(b, r, v)
+#define	nlm_get_bridge_pcibase(node)	\
+				nlm_pcicfg_base(XLP_IO_BRIDGE_OFFSET(node))
+#define	nlm_get_bridge_regbase(node)	\
+				(nlm_get_bridge_pcibase(node) + XLP_IO_PCI_HDRSZ)
 
 #endif
-
 #endif

Modified: user/jchandra/mips-xlp-support/sys/mips/nlm/hal/cop2.h
==============================================================================
--- user/jchandra/mips-xlp-support/sys/mips/nlm/hal/cop2.h	Sat Sep  3 07:15:14 2011	(r225362)
+++ user/jchandra/mips-xlp-support/sys/mips/nlm/hal/cop2.h	Sat Sep  3 08:03:25 2011	(r225363)
@@ -27,24 +27,24 @@
  *
  * NETLOGIC_BSD */
 
-#ifndef __NLM_COP2_H__
-#define __NLM_COP2_H__
+#ifndef __NLM_HAL_COP2_H__
+#define __NLM_HAL_COP2_H__
 
-#define XLP_COP2_TX_BUF_REG		0
-#define XLP_COP2_RX_BUF_REG		1
-#define XLP_COP2_TXMSGSTATUS_REG	2
-#define XLP_COP2_RXMSGSTATUS_REG	3
-#define XLP_COP2_MSGSTATUS1_REG		4
-#define XLP_COP2_MSGCONFIG_REG		5
-#define XLP_COP2_MSGCONFIG1_REG		6
-
-#define CROSSTHR_POPQ_EN		0x01
-#define VC0_POPQ_EN			0x02
-#define VC1_POPQ_EN			0x04
-#define VC2_POPQ_EN			0x08
-#define VC3_POPQ_EN			0x10
-#define ALL_VC_POPQ_EN			0x1E
-#define ALL_VC_CT_POPQ_EN		0x1F
+#define COP2_TX_BUF		0
+#define COP2_RX_BUF		1
+#define COP2_TXMSGSTATUS	2
+#define COP2_RXMSGSTATUS	3
+#define COP2_MSGSTATUS1		4
+#define COP2_MSGCONFIG		5
+#define COP2_MSGCONFIG1		6
+
+#define CROSSTHR_POPQ_EN	0x01
+#define VC0_POPQ_EN		0x02
+#define VC1_POPQ_EN		0x04
+#define VC2_POPQ_EN		0x08
+#define VC3_POPQ_EN		0x10
+#define ALL_VC_POPQ_EN		0x1E
+#define ALL_VC_CT_POPQ_EN	0x1F
 
 struct nlm_fmn_msg {
 	uint64_t msg[4];
@@ -61,8 +61,7 @@ static inline uint32_t nlm_read_c2_##nam
 	"mfc2	%0, $%1, %2\n"					\
 	".set	pop\n"						\
 	: "=r" (__rv)						\
-	: "i" (reg), "i" (sel)					\
-	);							\
+	: "i" (reg), "i" (sel));				\
 	return __rv;						\
 }								\
 								\
@@ -74,8 +73,7 @@ static inline void nlm_write_c2_##name(u
 	".set	mips64\n"					\
 	"mtc2	%0, $%1, %2\n"					\
 	".set	pop\n"						\
-	:: "r" (val), "i" (reg), "i" (sel)			\
-	);							\
+	: : "r" (val), "i" (reg), "i" (sel));			\
 } struct __hack
 
 #if (__mips == 64)
@@ -90,7 +88,7 @@ static inline uint64_t nlm_read_c2_##nam
 	"dmfc2	%0, $%1, %2\n"					\
 	".set	pop\n"						\
 	: "=r" (__rv)						\
-	: "i" (reg), "i" (sel) );				\
+	: "i" (reg), "i" (sel));				\
 	return __rv;						\
 }								\
 								\
@@ -102,7 +100,7 @@ static inline void nlm_write_c2_##name(u
 	".set	mips64\n"					\
 	"dmtc2	%0, $%1, %2\n"					\
 	".set	pop\n"						\
-	:: "r" (val), "i" (reg), "i" (sel) );			\
+	: : "r" (val), "i" (reg), "i" (sel));			\
 } struct __hack
 
 #else
@@ -121,15 +119,15 @@ static inline uint64_t nlm_read_c2_##nam
 	".set	pop\n"						\
 	: "=r"(__high), "=r"(__low)				\
 	: "i"(reg), "i"(sel)					\
-	: "$8" );						\
+	: "$8");						\
 								\
-	return (((uint64_t)__high << 32) | __low);		\
+	return ((uint64_t)__high << 32) | __low;		\
 }								\
 								\
 static inline void nlm_write_c2_##name(uint64_t val)		\
 {								\
-       uint32_t __high = val >> 32;				\
-       uint32_t __low = val & 0xffffffff;			\
+	uint32_t __high = val >> 32;				\
+	uint32_t __low = val & 0xffffffff;			\
 	__asm__ __volatile__ (					\
 	".set	push\n"						\
 	".set	noreorder\n"					\
@@ -140,113 +138,117 @@ static inline void nlm_write_c2_##name(u
 	"or	$8, $8, $9\n"					\
 	"dmtc2	$8, $%2, %3\n"					\
 	".set	pop\n"						\
-	:: "r"(__high), "r"(__low),  "i"(reg), "i"(sel)		\
-	:"$8", "$9");						\
+	: : "r"(__high), "r"(__low),  "i"(reg), "i"(sel)	\
+	: "$8", "$9");						\
 } struct __hack
 
 #endif
 
-NLM_DEFINE_COP2_ACCESSORS64(txbuf0, XLP_COP2_TX_BUF_REG, 0);
-NLM_DEFINE_COP2_ACCESSORS64(txbuf1, XLP_COP2_TX_BUF_REG, 1);
-NLM_DEFINE_COP2_ACCESSORS64(txbuf2, XLP_COP2_TX_BUF_REG, 2);
-NLM_DEFINE_COP2_ACCESSORS64(txbuf3, XLP_COP2_TX_BUF_REG, 3);
-
-NLM_DEFINE_COP2_ACCESSORS64(rxbuf0, XLP_COP2_RX_BUF_REG, 0);
-NLM_DEFINE_COP2_ACCESSORS64(rxbuf1, XLP_COP2_RX_BUF_REG, 1);
-NLM_DEFINE_COP2_ACCESSORS64(rxbuf2, XLP_COP2_RX_BUF_REG, 2);
-NLM_DEFINE_COP2_ACCESSORS64(rxbuf3, XLP_COP2_RX_BUF_REG, 3);
-
-NLM_DEFINE_COP2_ACCESSORS32(txmsgstatus, XLP_COP2_TXMSGSTATUS_REG, 0);
-NLM_DEFINE_COP2_ACCESSORS32(rxmsgstatus, XLP_COP2_RXMSGSTATUS_REG, 0);
-NLM_DEFINE_COP2_ACCESSORS32(msgstatus1, XLP_COP2_MSGSTATUS1_REG, 0);
-NLM_DEFINE_COP2_ACCESSORS32(msgconfig, XLP_COP2_MSGCONFIG_REG, 0);
-NLM_DEFINE_COP2_ACCESSORS32(msgconfig1, XLP_COP2_MSGCONFIG1_REG, 0);
+NLM_DEFINE_COP2_ACCESSORS64(txbuf0, COP2_TX_BUF, 0);
+NLM_DEFINE_COP2_ACCESSORS64(txbuf1, COP2_TX_BUF, 1);
+NLM_DEFINE_COP2_ACCESSORS64(txbuf2, COP2_TX_BUF, 2);
+NLM_DEFINE_COP2_ACCESSORS64(txbuf3, COP2_TX_BUF, 3);
+
+NLM_DEFINE_COP2_ACCESSORS64(rxbuf0, COP2_RX_BUF, 0);
+NLM_DEFINE_COP2_ACCESSORS64(rxbuf1, COP2_RX_BUF, 1);
+NLM_DEFINE_COP2_ACCESSORS64(rxbuf2, COP2_RX_BUF, 2);
+NLM_DEFINE_COP2_ACCESSORS64(rxbuf3, COP2_RX_BUF, 3);
+
+NLM_DEFINE_COP2_ACCESSORS32(txmsgstatus, COP2_TXMSGSTATUS, 0);
+NLM_DEFINE_COP2_ACCESSORS32(rxmsgstatus, COP2_RXMSGSTATUS, 0);
+NLM_DEFINE_COP2_ACCESSORS32(msgstatus1, COP2_MSGSTATUS1, 0);
+NLM_DEFINE_COP2_ACCESSORS32(msgconfig, COP2_MSGCONFIG, 0);
+NLM_DEFINE_COP2_ACCESSORS32(msgconfig1, COP2_MSGCONFIG1, 0);
 
 /* successful completion returns 1, else 0 */
-static __inline__ int nlm_msgsend(int val)
+static inline int
+nlm_msgsend(int val)
 {
 	int result;
 	__asm__ volatile (
-		".set push			\n"
-		".set noreorder			\n"
-		".set mips64			\n"
-		"move	$8, %1			\n"
-		"sync				\n"
-		"/* msgsnds	$9, $8 */	\n"
-		".word	0x4a084801		\n"
-		"move	%0, $9			\n"
-		".set pop			\n"
+		".set push\n"
+		".set noreorder\n"
+		".set mips64\n"
+		"move	$8, %1\n"
+		"sync\n"
+		"/* msgsnds	$9, $8 */\n"
+		".word	0x4a084801\n"
+		"move	%0, $9\n"
+		".set pop\n"
 		: "=r" (result)
 		: "r" (val)
-		: "$8", "$9"
-	);
+		: "$8", "$9");
 	return result;
 }
 
-static __inline__ int nlm_msgld(int vc)
+static inline int
+nlm_msgld(int vc)
 {
 	int val;
 	__asm__ volatile (
-		".set push			\n"
-		".set noreorder			\n"
-		".set mips64			\n"
-		"move	$8, %1			\n"
-		"/* msgld	$9, $8 */	\n"
-		".word 0x4a084802		\n"
-		"move	%0, $9			\n"
-		".set pop			\n"
+		".set push\n"
+		".set noreorder\n"
+		".set mips64\n"
+		"move	$8, %1\n"
+		"/* msgld	$9, $8 */\n"
+		".word 0x4a084802\n"
+		"move	%0, $9\n"
+		".set pop\n"
 		: "=r" (val)
 		: "r" (vc)
-		: "$8", "$9"
-	);
+		: "$8", "$9");
 	return val;
 }
 
-static __inline__ void nlm_msgwait(int vc)
+static inline void
+nlm_msgwait(int vc)
 {
 	__asm__ volatile (
-		".set push			\n"
-		".set noreorder			\n"
-		".set mips64			\n"
-		"move	$8, %0			\n"
-		"/* msgwait	$8 */		\n"
-		".word 0x4a080003		\n"
-		".set pop			\n"
-		:: "r" (vc)
-		: "$8"
-	);
+		".set push\n"
+		".set noreorder\n"
+		".set mips64\n"
+		"move	$8, %0\n"
+		"/* msgwait	$8 */\n"
+		".word 0x4a080003\n"
+		".set pop\n"
+		: : "r" (vc)
+		: "$8");
 }
 
 /* TODO this is not needed in n32 and n64 */
-static __inline uint32_t
+static inline uint32_t
 nlm_fmn_saveflags(void)
 {
 	uint32_t sr = mips_rd_status();
 
 	mips_wr_status((sr & ~MIPS_SR_INT_IE) | MIPS_SR_COP_2_BIT);
-	return (sr);
+	return sr;
 }
 
-static __inline void
+static inline void
 nlm_fmn_restoreflags(uint32_t sr)
 {
 
 	mips_wr_status(sr);
 }
 
-static __inline__ int nlm_fmn_msgsend(int dstid, int size, int swcode,
-		struct nlm_fmn_msg *m)
+static inline int
+nlm_fmn_msgsend(int dstid, int size, int swcode, struct nlm_fmn_msg *m)
 {
 	uint32_t flags, status;
 	int rv;
 
 	size -= 1;
 	flags = nlm_fmn_saveflags();
-	switch(size) {
-		case 3: nlm_write_c2_txbuf3(m->msg[3]);
-		case 2: nlm_write_c2_txbuf2(m->msg[2]);
-		case 1: nlm_write_c2_txbuf1(m->msg[1]);
-		case 0: nlm_write_c2_txbuf0(m->msg[0]);
+	switch (size) {
+	case 3:
+		nlm_write_c2_txbuf3(m->msg[3]);
+	case 2:
+		nlm_write_c2_txbuf2(m->msg[2]);
+	case 1:
+		nlm_write_c2_txbuf1(m->msg[1]);
+	case 0:
+		nlm_write_c2_txbuf0(m->msg[0]);
 	}
 
 	dstid |= ((swcode << 24) | (size << 16));
@@ -256,11 +258,11 @@ static __inline__ int nlm_fmn_msgsend(in
 		rv = nlm_read_c2_txmsgstatus();
 	nlm_fmn_restoreflags(flags);
 
-	return (rv);
+	return rv;
 }
 
-static __inline__ int nlm_fmn_msgrcv(int vc, int *srcid, int *size, int *code,
-    struct nlm_fmn_msg *m)
+static inline int
+nlm_fmn_msgrcv(int vc, int *srcid, int *size, int *code, struct nlm_fmn_msg *m)
 {
 	uint32_t status;
 	uint32_t msg_status, flags;
@@ -275,11 +277,15 @@ static __inline__ int nlm_fmn_msgrcv(int
 		*code = (msg_status >> 18) & 0xff;
 		*srcid = (msg_status >> 4) & 0xfff;
 		tmp_sz = *size - 1;
-		switch(tmp_sz) {
-			case 3: m->msg[3] = nlm_read_c2_rxbuf3();
-			case 2: m->msg[2] = nlm_read_c2_rxbuf2();
-			case 1: m->msg[1] = nlm_read_c2_rxbuf1();
-			case 0: m->msg[0] = nlm_read_c2_rxbuf0();
+		switch (tmp_sz) {
+		case 3:
+			m->msg[3] = nlm_read_c2_rxbuf3();
+		case 2:
+			m->msg[2] = nlm_read_c2_rxbuf2();
+		case 1:
+			m->msg[1] = nlm_read_c2_rxbuf1();
+		case 0:
+			m->msg[0] = nlm_read_c2_rxbuf0();
 		}
 	}
 	nlm_fmn_restoreflags(flags);
@@ -287,26 +293,8 @@ static __inline__ int nlm_fmn_msgrcv(int
 	return rv;
 }
 
-/**
- * nlm_fmn_cpu_init() initializes the per-h/w thread cop2 w.r.t the following
- * configuration parameters. It needs to be individually setup on each
- * hardware thread.
- *
- * int_vec - interrupt vector getting placed into msgconfig reg
- * ctpe - cross thread message pop enable. When set to 1, the thread (h/w cpu)
- *        associated where this cop2 register is setup, can pop messages
- *        intended for any other thread in the same core.
- * v0pe - VC0 pop message request mode enable. When set to 1, the thread
- * 	  can send pop requests to vc0.
- * v1pe - VC1 pop message request mode enable. When set to 1, the thread
- * 	  can send pop requests to vc1.
- * v2pe - VC2 pop message request mode enable. When set to 1, the thread
- * 	  can send pop requests to vc2.
- * v3pe - VC3 pop message request mode enable. When set to 1, the thread
- * 	  can send pop requests to vc3.
- */
-static __inline__ void nlm_fmn_cpu_init(int int_vec, int ctpe, int v0pe,
-    int v1pe, int v2pe, int v3pe)
+static inline void
+nlm_fmn_cpu_init(int int_vec, int ctpe, int v0pe, int v1pe, int v2pe, int v3pe)
 {
 	uint32_t val = nlm_read_c2_msgconfig();
 

Modified: user/jchandra/mips-xlp-support/sys/mips/nlm/hal/cpucontrol.h
==============================================================================
--- user/jchandra/mips-xlp-support/sys/mips/nlm/hal/cpucontrol.h	Sat Sep  3 07:15:14 2011	(r225362)
+++ user/jchandra/mips-xlp-support/sys/mips/nlm/hal/cpucontrol.h	Sat Sep  3 08:03:25 2011	(r225363)
@@ -27,43 +27,164 @@
  *
  * NETLOGIC_BSD */
 
-#ifndef __NLM_CPUCONTROL_H__
-#define __NLM_CPUCONTROL_H__
+#ifndef __NLM_HAL_CPUCONTROL_H__
+#define __NLM_HAL_CPUCONTROL_H__
 
-#define XLP_CPU_BLOCKID_IFU	0
-#define XLP_CPU_BLOCKID_ICU	1
-
-#define XLP_CPU_BLOCKID_IEU	2
-#define XLP_CPU_BLOCKID_LSU	3
-#define XLP_LSU_DEFEATURE	0x304
-#define XLP_LSU_CERRLOG_REGID 	0x09
-
-#define XLP_CPU_BLOCKID_MMU	4
-#define XLP_CPU_BLOCKID_PRF	5
-
-#define XLP_CPU_BLOCKID_SCH	7
-#define XLP_SCHED_DEFEATURE	0x700
-
-#define XLP_CPU_BLOCKID_SCU	8
-#define XLP_CPU_BLOCKID_FPU	9
-
-#define XLP_CPU_BLOCKID_MAP	10
+#define CPU_BLOCKID_IFU		0
+#define CPU_BLOCKID_ICU		1
+#define CPU_BLOCKID_IEU		2
+#define CPU_BLOCKID_LSU		3
+#define CPU_BLOCKID_MMU		4
+#define CPU_BLOCKID_PRF		5
+#define CPU_BLOCKID_SCH		7
+#define CPU_BLOCKID_SCU		8
+#define CPU_BLOCKID_FPU		9
+#define CPU_BLOCKID_MAP		10
+
+#define LSU_DEFEATURE		0x304
+#define LSU_CERRLOG_REGID	0x09
+#define SCHED_DEFEATURE		0x700
 
 /* Offsets of interest from the 'MAP' Block */
-#define XLP_BLKID_MAP_THREADMODE                    0x00
-#define XLP_BLKID_MAP_EXT_EBASE_ENABLE              0x04
-#define XLP_BLKID_MAP_CCDI_CONFIG                   0x08
-#define XLP_BLKID_MAP_THRD0_CCDI_STATUS             0x0c
-#define XLP_BLKID_MAP_THRD1_CCDI_STATUS             0x10
-#define XLP_BLKID_MAP_THRD2_CCDI_STATUS             0x14
-#define XLP_BLKID_MAP_THRD3_CCDI_STATUS             0x18
-#define XLP_BLKID_MAP_THRD0_DEBUG_MODE              0x1c
-#define XLP_BLKID_MAP_THRD1_DEBUG_MODE              0x20
-#define XLP_BLKID_MAP_THRD2_DEBUG_MODE              0x24
-#define XLP_BLKID_MAP_THRD3_DEBUG_MODE              0x28
-#define XLP_BLKID_MAP_MISC_STATE                    0x60
-#define XLP_BLKID_MAP_DEBUG_READ_CTL                0x64
-#define XLP_BLKID_MAP_DEBUG_READ_REG0               0x68
-#define XLP_BLKID_MAP_DEBUG_READ_REG1               0x6c
+#define MAP_THREADMODE			0x00
+#define MAP_EXT_EBASE_ENABLE		0x04
+#define MAP_CCDI_CONFIG			0x08
+#define MAP_THRD0_CCDI_STATUS		0x0c
+#define MAP_THRD1_CCDI_STATUS		0x10
+#define MAP_THRD2_CCDI_STATUS		0x14
+#define MAP_THRD3_CCDI_STATUS		0x18
+#define MAP_THRD0_DEBUG_MODE		0x1c
+#define MAP_THRD1_DEBUG_MODE		0x20
+#define MAP_THRD2_DEBUG_MODE		0x24
+#define MAP_THRD3_DEBUG_MODE		0x28
+#define MAP_MISC_STATE			0x60
+#define MAP_DEBUG_READ_CTL		0x64
+#define MAP_DEBUG_READ_REG0		0x68
+#define MAP_DEBUG_READ_REG1		0x6c
+
+#define MMU_SETUP		0x400
+#define MMU_LFSRSEED		0x401
+#define MMU_HPW_NUM_PAGE_LVL	0x410
+#define MMU_PGWKR_PGDBASE	0x411
+#define MMU_PGWKR_PGDSHFT	0x412
+#define MMU_PGWKR_PGDMASK	0x413
+#define MMU_PGWKR_PUDSHFT	0x414
+#define MMU_PGWKR_PUDMASK	0x415
+#define MMU_PGWKR_PMDSHFT	0x416
+#define MMU_PGWKR_PMDMASK	0x417
+#define MMU_PGWKR_PTESHFT	0x418
+#define MMU_PGWKR_PTEMASK	0x419
+
+
+#if !defined(LOCORE) && !defined(__ASSEMBLY__)
+#if defined(__mips_n64) || defined(__mips_n32)
+static __inline uint64_t
+nlm_mfcr(uint32_t reg)
+{
+	uint64_t res;
+
+	__asm__ __volatile__(
+	    ".set	push\n\t"
+	    ".set	noreorder\n\t"
+	    "move	$9, %1\n\t"
+	    ".word	0x71280018\n\t"  /* mfcr $8, $9 */
+	    "move	%0, $8\n\t"
+	    ".set	pop\n"
+	    : "=r" (res) : "r"(reg)
+	    : "$8", "$9"
+	);
+	return (res);
+}
+
+static __inline void
+nlm_mtcr(uint32_t reg, uint64_t value)
+{
+	__asm__ __volatile__(
+	    ".set	push\n\t"
+	    ".set	noreorder\n\t"
+	    "move	$8, %0\n"
+	    "move	$9, %1\n"
+	    ".word	0x71280019\n"    /* mtcr $8, $9  */
+	    ".set	pop\n"
+	    :
+	    : "r" (value), "r" (reg)
+	    : "$8", "$9"
+	);
+}
+
+#else /* !(defined(__mips_n64) || defined(__mips_n32)) */
+
+static __inline__  uint64_t
+nlm_mfcr(uint32_t reg)
+{
+        uint32_t hi, lo;
+
+        __asm__ __volatile__ (
+                ".set push\n"
+                ".set mips64\n"
+                "move   $8, %2\n"
+                ".word  0x71090018\n"
+		"nop	\n"
+                "dsra32 %0, $9, 0\n"
+                "sll    %1, $9, 0\n"
+                ".set pop\n"
+                : "=r"(hi), "=r"(lo)
+                : "r"(reg) : "$8", "$9");
+
+        return (((uint64_t)hi) << 32) | lo;
+}
+
+static __inline__  void
+nlm_mtcr(uint32_t reg, uint64_t val)
+{
+	uint32_t hi, lo;
+
+	hi = val >> 32;
+	lo = val & 0xffffffff;
+
+        __asm__ __volatile__ (
+                ".set push\n"
+                ".set mips64\n"
+                "move   $9, %0\n"
+                "dsll32 $9, %1, 0\n"
+                "dsll32 $8, %0, 0\n"
+                "dsrl32 $9, $9, 0\n"
+                "or     $9, $9, $8\n"
+                "move   $8, %2\n"
+                ".word  0x71090019\n"
+		"nop	\n"
+                ".set pop\n"
+                ::"r"(hi), "r"(lo), "r"(reg)
+                : "$8", "$9");
+}
+#endif /* (defined(__mips_n64) || defined(__mips_n32)) */
+
+/* hashindex_en = 1 to enable hash mode, hashindex_en=0 to disable
+ * global_mode = 1 to enable global mode, global_mode=0 to disable
+ * clk_gating = 0 to enable clock gating, clk_gating=1 to disable
+ */
+static __inline__ void nlm_mmu_setup(int hashindex_en, int global_mode,
+		int clk_gating)
+{
+	uint32_t mmusetup = 0;
+
+	mmusetup |= (hashindex_en << 13);
+	mmusetup |= (clk_gating << 3);
+	mmusetup |= (global_mode << 0);
+	nlm_mtcr(MMU_SETUP, mmusetup);
+}
+
+static __inline__ void nlm_mmu_lfsr_seed (int thr0_seed, int thr1_seed,
+		int thr2_seed, int thr3_seed)
+{
+	uint32_t seed = nlm_mfcr(MMU_LFSRSEED);
+
+	seed |= ((thr3_seed & 0x7f) << 23);
+	seed |= ((thr2_seed & 0x7f) << 16);
+	seed |= ((thr1_seed & 0x7f) << 7);
+	seed |= ((thr0_seed & 0x7f) << 0);
+	nlm_mtcr(MMU_LFSRSEED, seed);
+}
 
+#endif /* __ASSEMBLY__ */
 #endif /* __NLM_CPUCONTROL_H__ */

Modified: user/jchandra/mips-xlp-support/sys/mips/nlm/hal/fmn.c
==============================================================================
--- user/jchandra/mips-xlp-support/sys/mips/nlm/hal/fmn.c	Sat Sep  3 07:15:14 2011	(r225362)
+++ user/jchandra/mips-xlp-support/sys/mips/nlm/hal/fmn.c	Sat Sep  3 08:03:25 2011	(r225363)
@@ -31,10 +31,10 @@
 #include <mips/nlm/hal/mips-extns.h>
 #include <mips/nlm/hal/mmio.h>
 #include <mips/nlm/hal/iomap.h>
+#include <mips/nlm/hal/cpuinfo.h>
 #include <mips/nlm/hal/fmn.h>
 #include <sys/systm.h>
 
-uint32_t bad_xlp_num_nodes = 4;
 /* XLP can take upto 16K of FMN messages per hardware queue, as spill.
 * But, configuring all 16K causes the total spill memory to required
 * to blow upto 192MB for single chip configuration, and 768MB in four
@@ -64,27 +64,7 @@ uint64_t nlm_cms_spill_total_messages = 
 * For all 4 nodes, there are 18*4 = 72 FMN stations
 */
 uint32_t nlm_cms_total_stations = 18 * 4 /*xlp_num_nodes*/;
-uint32_t cms_onchip_seg_availability[XLP_CMS_ON_CHIP_PER_QUEUE_SPACE];
-
-int nlm_cms_verify_credit_config (int spill_en, int tot_credit)
-{
-	/* Note: In XLP there seem to be no mechanism to read back
-	 * the credit count that has been programmed into a sid / did pair;
-	 * since we have only one register 0x2000 to read.
-	 * Hence it looks like all credit mgmt/verification needs to
-	 * be done by software. Software could keep track of total credits
-	 * getting programmed and verify it from this function.
-	 */
-
-	if (spill_en) {
-		/* TODO */
-	}
-
-	if (tot_credit > (XLP_CMS_ON_CHIP_MESG_SPACE*bad_xlp_num_nodes))
-		return 1; /* credits overflowed - should not happen */
-
-	return 0;
-}
+uint32_t cms_onchip_seg_availability[CMS_ON_CHIP_PER_QUEUE_SPACE];
 
 /**
  * Takes inputs as node, queue_size and maximum number of queues.
@@ -159,7 +139,7 @@ void nlm_cms_setup_credits(uint64_t base
 	uint32_t val;
 
 	val = ((credit << 24) | (destid << 12) | (srcid << 0));
-	nlm_wreg_cms(base, XLP_CMS_OUTPUTQ_CREDIT_CFG_REG, val);
+	nlm_write_cms_reg(base, CMS_OUTPUTQ_CREDIT_CFG, val);
 
 }
 
@@ -178,93 +158,93 @@ int nlm_cms_config_onchip_queue (uint64_
 
 #if 0
 	/* configure credits for src cpu0, on this queue */
-	nlm_cms_setup_credits(base, qid, XLP_CMS_CPU0_SRC_STID,
-		XLP_CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
+	nlm_cms_setup_credits(base, qid, CMS_CPU0_SRC_STID,
+		CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
 			nlm_cms_spill_total_messages));
 
 	/* configure credits for src cpu1, on this queue */
-	nlm_cms_setup_credits(base, qid, XLP_CMS_CPU1_SRC_STID,
-		XLP_CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
+	nlm_cms_setup_credits(base, qid, CMS_CPU1_SRC_STID,
+		CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
 			nlm_cms_spill_total_messages));
 
 	/* configure credits for src cpu2, on this queue */
-	nlm_cms_setup_credits(base, qid, XLP_CMS_CPU2_SRC_STID,
-		XLP_CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
+	nlm_cms_setup_credits(base, qid, CMS_CPU2_SRC_STID,
+		CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
 			nlm_cms_spill_total_messages));
 
 	/* configure credits for src cpu3, on this queue */
-	nlm_cms_setup_credits(base, qid, XLP_CMS_CPU3_SRC_STID,
-		XLP_CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
+	nlm_cms_setup_credits(base, qid, CMS_CPU3_SRC_STID,
+		CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
 			nlm_cms_spill_total_messages));
 
 	/* configure credits for src cpu4, on this queue */
-	nlm_cms_setup_credits(base, qid, XLP_CMS_CPU4_SRC_STID,
-		XLP_CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
+	nlm_cms_setup_credits(base, qid, CMS_CPU4_SRC_STID,
+		CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
 			nlm_cms_spill_total_messages));
 
 	/* configure credits for src cpu5, on this queue */
-	nlm_cms_setup_credits(base, qid, XLP_CMS_CPU5_SRC_STID,
-		XLP_CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
+	nlm_cms_setup_credits(base, qid, CMS_CPU5_SRC_STID,
+		CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
 			nlm_cms_spill_total_messages));
 
 	/* configure credits for src cpu6, on this queue */
-	nlm_cms_setup_credits(base, qid, XLP_CMS_CPU6_SRC_STID,
-		XLP_CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
+	nlm_cms_setup_credits(base, qid, CMS_CPU6_SRC_STID,
+		CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
 			nlm_cms_spill_total_messages));
 
 	/* configure credits for src cpu7, on this queue */
-	nlm_cms_setup_credits(base, qid, XLP_CMS_CPU7_SRC_STID,
-		XLP_CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
+	nlm_cms_setup_credits(base, qid, CMS_CPU7_SRC_STID,
+		CMS_DEFAULT_CREDIT(nlm_cms_total_stations,
 			nlm_cms_spill_total_messages));

*** DIFF OUTPUT TRUNCATED AT 1000 LINES ***



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