From owner-freebsd-hardware Wed May 28 15:24:50 1997 Return-Path: Received: (from root@localhost) by hub.freebsd.org (8.8.5/8.8.5) id PAA07365 for hardware-outgoing; Wed, 28 May 1997 15:24:50 -0700 (PDT) Received: from Sisyphos.MI.Uni-Koeln.DE (Sisyphos.MI.Uni-Koeln.DE [134.95.212.10]) by hub.freebsd.org (8.8.5/8.8.5) with SMTP id PAA07356; Wed, 28 May 1997 15:24:41 -0700 (PDT) Received: from x14.mi.uni-koeln.de (annexr3-15.slip.Uni-Koeln.DE) by Sisyphos.MI.Uni-Koeln.DE with SMTP id AA17138 (5.67b/IDA-1.5); Thu, 29 May 1997 00:24:10 +0200 Received: (from se@localhost) by x14.mi.uni-koeln.de (8.8.5/8.6.9) id AAA00469; Thu, 29 May 1997 00:24:08 +0200 (CEST) X-Face: " Date: Thu, 29 May 1997 00:24:06 +0200 From: Stefan Esser To: Satoshi Asami Cc: kato@eclogite.eps.nagoya-u.ac.jp, roberto@keltia.freenix.fr, hardware@FreeBSD.ORG, Stefan Esser Subject: Re: Intel Pentium II released References: <199705281354.WAA19773@gneiss.eps.nagoya-u.ac.jp> <199705282105.OAA06447@vader.cs.berkeley.edu> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii X-Mailer: Mutt 0.74 In-Reply-To: <199705282105.OAA06447@vader.cs.berkeley.edu>; from Satoshi Asami on Wed, May 28, 1997 at 02:05:21PM -0700 Sender: owner-hardware@FreeBSD.ORG X-Loop: FreeBSD.org Precedence: bulk On May 28, Satoshi Asami wrote: > * > Could it that the motherboard does not support all of K6's new > * > features? (I heard you need a new BIOS for that if you have an older > * > version of some motherboards.) > * > * Could someone explain how to enable K6's `new feature'? > The AMD-K6(TM) processor, Socket 7 bus compatible by design, enables > PC manufacturers and resellers to deliver affordable, top-to-bottom PC > solutions. For existing Socket 7 motherboards, certain modifications > may be necessary to ensure proper voltage settings and BIOS support." > ^^^^^^^^^^^^ > I'm not sure what this means. Guess this is the write-allocate feature of the primary cache, which is off by default. There is an additional bit in the TLB, that indicates a read on some page could be cached. The CPU then knows that it may cache writes to that page, even if the line is not currently in cache (-> write-allocate). There is a base/limit register that allows to specify some address region (normally system D-RAM) as cacheable, additionally. This lets all writes in that area be cached. Both features are off, by default. (There was another feature like the first one above, but based on a hint found in the cache line, if I remember correctly. Something like, write-allocate, if the line had been valid and cacheable, even if it was flushed because of a bus snoop and is not valid right now ...) These features can be enabled by a knowledgable BIOS, or from the OS. I have the docs at home, the details are all in the PDF data book found on the AMD web site ... Regards, STefan PS: Write-allocate should of course make a big difference for block copies, which would explain the very different results reported.