Date: Mon, 5 Jan 2015 20:26:39 -0700 From: Warner Losh <imp@bsdimp.com> To: Ian Lepore <ian@FreeBSD.org> Cc: Warner Losh <imp@freebsd.org>, "freebsd-mips@freebsd.org" <freebsd-mips@freebsd.org>, John Baldwin <jhb@freebsd.org> Subject: Re: interrupt muxes, bus memory space and other fun amusing things Message-ID: <3AB1B833-6D17-44C4-B588-8CEAB0CA4A42@bsdimp.com> In-Reply-To: <1420514079.14601.7.camel@freebsd.org> References: <CAJ-Vmo=LqZ6Z9oYU5Usv4rHY4AffZPy4QBqwN4onr2STq5OfMg@mail.gmail.com> <5F7CBB50-6C91-49C9-BF69-301496DDE792@bsdimp.com> <CAJ-VmokGtqFZ=sDUgetwEdoGagR7hz1Rfys_ph%2BnbtdRuFsBNQ@mail.gmail.com> <9F6D585C-7590-4D25-879B-A76D8A959E01@bsdimp.com> <1420514079.14601.7.camel@freebsd.org>
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--Apple-Mail=_5A80BF58-FCAC-4A55-8550-F708A28358CB Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=utf-8 > On Jan 5, 2015, at 8:14 PM, Ian Lepore <ian@FreeBSD.org> wrote: >=20 > On Mon, 2015-01-05 at 20:10 -0700, Warner Losh wrote: >>> On Jan 5, 2015, at 1:31 PM, Adrian Chadd <adrian@FreeBSD.org> wrote: >>>=20 >>> On 5 January 2015 at 08:41, Warner Losh <imp@bsdimp.com> wrote: >>>>=20 >>>>> So if I were Linux, I'd just implement a mux that pretends to = trigger >>>>> interrupts in a much bigger IRQ space. Ie, they map IP0..IP7 to >>>>> irq0..7, then they pick another IRQ range for the AHB interrupts, = and >>>>> another IRQ range for the IP2/IP3 interrupt mux. They have a >>>>> hard-coded mux that takes care of triggering the software IRQ = based on >>>>> the hardware interrupt and mux register contents. >>>>>=20 >>>>> So, how should I approach this? >>>>=20 >>>> Same way. You=E2=80=99d create an interrupt device that registers = an interrupt >>>> for the mux, then farms it out based on the contents of the = registers. >>>> The MIPS interrupt handler might need some work (arm did) to >>>> allow this to happen, but it isn=E2=80=99t super difficult (though = IIRc it is tedious). >>>=20 >>> Ok. So I can do that, but then devices hang off of which bus? = nexus0? >>> Or this mux? >>>=20 >>> Can I create a mux bus to hang things off of that just pass all the >>> memory region requests up to the parent bus (nexus in this case) ? >>=20 >> The hard part is mapping an interrupt provided by a mux to a resource >> number. However, we already do this for the =E2=80=98hard wired=E2=80=99= interrupts >> that are muxed through APIC or PIC controllers on x86. I fail to see = how >> this is any different, apart (perhaps) from the need to do things = dynamically >> in some way. >>=20 >> Warner >>=20 >=20 > It sounds like mips is ready for intrng. Which would then give us = ppc, > arm, and mips all with a conceptually-similar intrng-like layer for > handling non-hierarchical interrupt sources and controllers and = mapping > between rman and hardware ideas of interrupt number. Hmmm. This = would > be the time to argue for a nice shiny new MI intrng implementation... > except that we can't quite drive even the arm-only version to > completion. Maybe now=E2=80=99s the time? Warner --Apple-Mail=_5A80BF58-FCAC-4A55-8550-F708A28358CB Content-Transfer-Encoding: 7bit Content-Disposition: attachment; filename=signature.asc Content-Type: application/pgp-signature; name=signature.asc Content-Description: Message signed with OpenPGP using GPGMail -----BEGIN PGP SIGNATURE----- Comment: GPGTools - https://gpgtools.org iQIcBAEBCgAGBQJUq1XwAAoJEGwc0Sh9sBEAPfYQALK8VaS+NpppE60yn50gkxEm rU+w+i4yMg+R7yhTZhytNMuIL0BA0w9BakGmmD9K0A3JXbF7aHBt+w/LwWwVOAfH 025rZppZK2lveboFQ3t2xngsdwFC6KmsSY6tFsA1SR66HFeO29Bh2fisxtNmqdZP uvyZ1/J7nPGphr+3PPx8e/lA+qfijeP2hfe6axYsiuYKH6sb0qB0A/wcM/isznDa L5hdmKVYdryk0TSbgEbHpz4IhaWx+zdHdj9ULi7G8bZhq3qF/raNrrm32bSS5y8j Uroq8BlAVOKGUxOQqHdlwsnj2wZpJrTStWbt7eYrUOi7okv6VTc5ye9oGo37T9WS 9nh27DsOPfNzJHMA3sDjTUEM7tI84awpG/4oSAlveQTQI26xE2ziqXOWhF4kzJOc IKEv+22ikjsxMIlbCLu5ECfYpsFqq2KMhEIikAUcAUfV7tMl1/cOjAL37yXyC9JU ABlFUYJ6lYbQQDKnnT/icsXeTOLioyV3ZixdqTE12bJY25IMeftLlWENqyTTFCDa 5bH1qkNgPbzRrosBm3Y6GO4w5YEVIskbASXFCASGVGFzU+Iz43fFQtQC2e3iQWdr rvX2xzMIUvQQwEmKucJHsyCcxgQRX0whsSegDNJ7vjNYiq3UBLhPLs78+EKVOaBI BoBQwUTWN80zcnJUz9g6 =tWdH -----END PGP SIGNATURE----- --Apple-Mail=_5A80BF58-FCAC-4A55-8550-F708A28358CB--
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