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Date:      Sun, 02 Feb 1997 23:43:06 +0100
From:      Eric.Schenk@dna.lth.se
To:        "David S. Miller" <davem@jenolan.rutgers.edu>
Cc:        Eric.Schenk@dna.lth.se, terry@lambert.org, michaelh@cet.co.jp, netdev@roxanne.nuclecu.unam.mx, roque@di.fc.ul.pt, freebsd-smp@freebsd.org, smpdev@roxanne.nuclecu.unam.mx
Subject:   Re: SMP 
Message-ID:  <199702022243.XAA10311@regin>
In-Reply-To: Your message of "Sun, 02 Feb 1997 16:44:36 EST." <199702022144.QAA19640@jenolan.caipgeneral> 

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"David S. Miller" <davem@jenolan.rutgers.edu> writes:
>I mean Jesus Christ, how do you implement a read/writer lock for
>crying out loud with that problem?  If I understand the issue
>properly, this means you'd have to lock the entire bus for every
>_access_ to any piece of the lock structure.  I'm glad my primary
>platform isn't the Intel, but it actually a fun chip to optimize
>assembly for.

ARGHH! If Intel wanted to play the multi-processor game they should
have at least talked to someone who had been paying attention to the
last 20 years of research in the area. Just how badly screwed are the
Intel chips in this respect? My impression was that they at least
where suppose to give us cache-coherency. I don't suppose that
it happens to be documented when we actually get it and when we don't?
Or we going to have to discover this the hard way as we progressively
try to move better parallel/distibuted algorithms?

-- 
Eric Schenk                               www: http://www.dna.lth.se/~erics
Dept. of Comp. Sci., Lund University          email: Eric.Schenk@dna.lth.se
Box 118, S-221 00 LUND, Sweden   fax: +46-46 13 10 21  ph: +46-46 222 96 38



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