From owner-svn-src-head@FreeBSD.ORG Mon May 23 21:00:57 2011 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id EFA09106564A; Mon, 23 May 2011 21:00:56 +0000 (UTC) (envelope-from yongari@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id E01528FC18; Mon, 23 May 2011 21:00:56 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id p4NL0uTY037624; Mon, 23 May 2011 21:00:56 GMT (envelope-from yongari@svn.freebsd.org) Received: (from yongari@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id p4NL0uNN037622; Mon, 23 May 2011 21:00:56 GMT (envelope-from yongari@svn.freebsd.org) Message-Id: <201105232100.p4NL0uNN037622@svn.freebsd.org> From: Pyun YongHyeon Date: Mon, 23 May 2011 21:00:56 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r222226 - head/sys/dev/msk X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 23 May 2011 21:00:57 -0000 Author: yongari Date: Mon May 23 21:00:56 2011 New Revision: 222226 URL: http://svn.freebsd.org/changeset/base/222226 Log: Make sure to enable all clocks before accessing registers. Releasing PHY from power down/COMA is done after enabling all clocks. While I'm here remove unnecessary controller reset. Modified: head/sys/dev/msk/if_msk.c Modified: head/sys/dev/msk/if_msk.c ============================================================================== --- head/sys/dev/msk/if_msk.c Mon May 23 21:00:37 2011 (r222225) +++ head/sys/dev/msk/if_msk.c Mon May 23 21:00:56 2011 (r222226) @@ -1212,37 +1212,30 @@ msk_phy_power(struct msk_softc *sc, int */ CSR_WRITE_1(sc, B2_Y2_CLK_GATE, val); - val = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); - val &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); + our = CSR_PCI_READ_4(sc, PCI_OUR_REG_1); + our &= ~(PCI_Y2_PHY1_POWD | PCI_Y2_PHY2_POWD); if (sc->msk_hw_id == CHIP_ID_YUKON_XL) { if (sc->msk_hw_rev > CHIP_REV_YU_XL_A1) { /* Deassert Low Power for 1st PHY. */ - val |= PCI_Y2_PHY1_COMA; + our |= PCI_Y2_PHY1_COMA; if (sc->msk_num_port > 1) - val |= PCI_Y2_PHY2_COMA; + our |= PCI_Y2_PHY2_COMA; } } - /* Release PHY from PowerDown/COMA mode. */ - CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, val); - switch (sc->msk_hw_id) { - case CHIP_ID_YUKON_EC_U: - case CHIP_ID_YUKON_EX: - case CHIP_ID_YUKON_FE_P: - case CHIP_ID_YUKON_UL_2: - case CHIP_ID_YUKON_OPT: - CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_OFF); - - /* Enable all clocks. */ - CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); - our = CSR_PCI_READ_4(sc, PCI_OUR_REG_4); - our &= (PCI_FORCE_ASPM_REQUEST|PCI_ASPM_GPHY_LINK_DOWN| - PCI_ASPM_INT_FIFO_EMPTY|PCI_ASPM_CLKRUN_REQUEST); + if (sc->msk_hw_id == CHIP_ID_YUKON_EC_U || + sc->msk_hw_id == CHIP_ID_YUKON_EX || + sc->msk_hw_id >= CHIP_ID_YUKON_FE_P) { + val = CSR_PCI_READ_4(sc, PCI_OUR_REG_4); + val &= (PCI_FORCE_ASPM_REQUEST | + PCI_ASPM_GPHY_LINK_DOWN | PCI_ASPM_INT_FIFO_EMPTY | + PCI_ASPM_CLKRUN_REQUEST); /* Set all bits to 0 except bits 15..12. */ - CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, our); - our = CSR_PCI_READ_4(sc, PCI_OUR_REG_5); - our &= PCI_CTL_TIM_VMAIN_AV_MSK; - CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, our); + CSR_PCI_WRITE_4(sc, PCI_OUR_REG_4, val); + val = CSR_PCI_READ_4(sc, PCI_OUR_REG_5); + val &= PCI_CTL_TIM_VMAIN_AV_MSK; + CSR_PCI_WRITE_4(sc, PCI_OUR_REG_5, val); CSR_PCI_WRITE_4(sc, PCI_CFG_REG_1, 0); + CSR_WRITE_2(sc, B0_CTST, Y2_HW_WOL_ON); /* * Disable status race, workaround for * Yukon EC Ultra & Yukon EX. @@ -1251,10 +1244,10 @@ msk_phy_power(struct msk_softc *sc, int val |= GLB_GPIO_STAT_RACE_DIS; CSR_WRITE_4(sc, B2_GP_IO, val); CSR_READ_4(sc, B2_GP_IO); - break; - default: - break; } + /* Release PHY from PowerDown/COMA mode. */ + CSR_PCI_WRITE_4(sc, PCI_OUR_REG_1, our); + for (i = 0; i < sc->msk_num_port; i++) { CSR_WRITE_2(sc, MR_ADDR(i, GMAC_LINK_CTRL), GMLC_RST_SET); @@ -1302,8 +1295,6 @@ mskc_reset(struct msk_softc *sc) uint32_t val; int i, initram; - CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); - /* Disable ASF. */ if (sc->msk_hw_id == CHIP_ID_YUKON_EX) { status = CSR_READ_2(sc, B28_Y2_ASF_HCU_CCSR); @@ -1712,6 +1703,9 @@ mskc_attach(device_t dev) } } + /* Enable all clocks before accessing any registers. */ + CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); + CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); sc->msk_hw_id = CSR_READ_1(sc, B2_CHIP_ID); sc->msk_hw_rev = (CSR_READ_1(sc, B2_MAC_CFG) >> 4) & 0x0f; @@ -1752,9 +1746,6 @@ mskc_attach(device_t dev) resource_int_value(device_get_name(dev), device_get_unit(dev), "int_holdoff", &sc->msk_int_holdoff); - /* Soft reset. */ - CSR_WRITE_2(sc, B0_CTST, CS_RST_SET); - CSR_WRITE_2(sc, B0_CTST, CS_RST_CLR); sc->msk_pmd = CSR_READ_1(sc, B2_PMD_TYP); /* Check number of MACs. */ sc->msk_num_port = 1; @@ -2969,6 +2960,7 @@ mskc_resume(device_t dev) MSK_LOCK(sc); + CSR_PCI_WRITE_4(sc, PCI_OUR_REG_3, 0); mskc_reset(sc); for (i = 0; i < sc->msk_num_port; i++) { if (sc->msk_if[i] != NULL && sc->msk_if[i]->msk_ifp != NULL &&