From owner-svn-src-stable-12@freebsd.org Wed Mar 4 21:12:09 2020 Return-Path: Delivered-To: svn-src-stable-12@mailman.nyi.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2610:1c1:1:606c::19:1]) by mailman.nyi.freebsd.org (Postfix) with ESMTP id C901B25190F; Wed, 4 Mar 2020 21:12:09 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from mxrelay.nyi.freebsd.org (mxrelay.nyi.freebsd.org [IPv6:2610:1c1:1:606c::19:3]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) server-signature RSA-PSS (4096 bits) client-signature RSA-PSS (4096 bits) client-digest SHA256) (Client CN "mxrelay.nyi.freebsd.org", Issuer "Let's Encrypt Authority X3" (verified OK)) by mx1.freebsd.org (Postfix) with ESMTPS id 48Xmm93dPTz4C5y; Wed, 4 Mar 2020 21:12:09 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mxrelay.nyi.freebsd.org (Postfix) with ESMTPS id 5EE2F24425; Wed, 4 Mar 2020 21:12:09 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id 024LC9kA029930; Wed, 4 Mar 2020 21:12:09 GMT (envelope-from manu@FreeBSD.org) Received: (from manu@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id 024LC8sn029928; Wed, 4 Mar 2020 21:12:08 GMT (envelope-from manu@FreeBSD.org) Message-Id: <202003042112.024LC8sn029928@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: manu set sender to manu@FreeBSD.org using -f From: Emmanuel Vadot Date: Wed, 4 Mar 2020 21:12:08 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-stable@freebsd.org, svn-src-stable-12@freebsd.org Subject: svn commit: r358647 - in stable/12/sys/arm64/rockchip: . clk X-SVN-Group: stable-12 X-SVN-Commit-Author: manu X-SVN-Commit-Paths: in stable/12/sys/arm64/rockchip: . clk X-SVN-Commit-Revision: 358647 X-SVN-Commit-Repository: base MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-stable-12@freebsd.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: SVN commit messages for only the 12-stable src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 04 Mar 2020 21:12:09 -0000 Author: manu Date: Wed Mar 4 21:12:08 2020 New Revision: 358647 URL: https://svnweb.freebsd.org/changeset/base/358647 Log: MFC r355624, r355852-r355853 r355624: arm64: rk3328: Add the *clk_peri_niu clocks Those clocks are always enable by default and are not really explained in the TRM but the reason we had them is that they have the periph clock as a parent and those parent should never be disable which can happen if we disable all the childs. The current childs are the sd/emmc/sdio clocks so the board will hang if we disable them. r355852: arm64: rockchip: rk_pinctrl: Fix clear bits in SYSCON_MODIFY r351187 change the SYSCON_WRITE to SYSCON_MODIFY but didn't changed the mask variable that used to hold the bitmask in the upper 16 bits of the register that control which bits are changed. So we ended up clearing bit from the upper 16bits half which are always 0 after a read. Use the correct bit mask for bits that we want to clear. r355853: arm64: rockchip: rk_gpio: Fix pin number The maxpin counter starts at 0, fix one by one error. This is still not totally correct for some banks in some SoC that have fewer pins but this will be dealt with in another commit. Modified: stable/12/sys/arm64/rockchip/clk/rk3328_cru.c stable/12/sys/arm64/rockchip/rk_gpio.c stable/12/sys/arm64/rockchip/rk_pinctrl.c Directory Properties: stable/12/ (props changed) Modified: stable/12/sys/arm64/rockchip/clk/rk3328_cru.c ============================================================================== --- stable/12/sys/arm64/rockchip/clk/rk3328_cru.c Wed Mar 4 21:06:29 2020 (r358646) +++ stable/12/sys/arm64/rockchip/clk/rk3328_cru.c Wed Mar 4 21:12:08 2020 (r358647) @@ -103,6 +103,8 @@ static struct rk_cru_gate rk3328_gates[] = { CRU_GATE(HCLK_SDMMC, "hclk_sdmmc", "hclk_peri", 0x24C, 0) CRU_GATE(HCLK_SDIO, "hclk_sdio", "hclk_peri", 0x24C, 1) CRU_GATE(HCLK_EMMC, "hclk_emmc", "hclk_peri", 0x24C, 2) + CRU_GATE(0, "hclk_peri_niu", "hclk_peri", 0x24C, 12) + CRU_GATE(0, "pclk_peri_niu", "hclk_peri", 0x24C, 13) CRU_GATE(HCLK_SDMMC_EXT, "hclk_sdmmc_ext", "hclk_peri", 0x24C, 15) }; Modified: stable/12/sys/arm64/rockchip/rk_gpio.c ============================================================================== --- stable/12/sys/arm64/rockchip/rk_gpio.c Wed Mar 4 21:06:29 2020 (r358646) +++ stable/12/sys/arm64/rockchip/rk_gpio.c Wed Mar 4 21:12:08 2020 (r358647) @@ -196,7 +196,7 @@ rk_gpio_pin_max(device_t dev, int *maxpin) { /* Each bank have always 32 pins */ - *maxpin = 32; + *maxpin = 31; return (0); } Modified: stable/12/sys/arm64/rockchip/rk_pinctrl.c ============================================================================== --- stable/12/sys/arm64/rockchip/rk_pinctrl.c Wed Mar 4 21:06:29 2020 (r358646) +++ stable/12/sys/arm64/rockchip/rk_pinctrl.c Wed Mar 4 21:12:08 2020 (r358647) @@ -883,7 +883,7 @@ rk_pinctrl_configure_pin(struct rk_pinctrl_softc *sc, reg += bank * 0x10 + ((pin / 8) * 0x4); bit = (pin % 8) * 2; - mask = (0x3 << bit) << 16; + mask = (0x3 << bit); SYSCON_MODIFY_4(syscon, reg, mask, bias << bit | (mask << 16)); } @@ -891,7 +891,7 @@ rk_pinctrl_configure_pin(struct rk_pinctrl_softc *sc, rv = rk_pinctrl_parse_drive(sc, pin_conf, bank, subbank, &drive, ®); if (rv == 0) { bit = (pin % 8) * 2; - mask = (0x3 << bit) << 16; + mask = (0x3 << bit); SYSCON_MODIFY_4(syscon, reg, mask, drive << bit | (mask << 16)); }