version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT) for ; Tue, 25 Nov 2025 14:12:16 +0200 (EET) (envelope-from titus@edc.ro) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=edc.ro; s=mail; t=1764072736; bh=HpnaW5ExPVZs19kBWCjytLlNWq7gk4l1t20f+iTPdcg=; h=From:Subject:Date:To; b=oxaQFL7Qv4OmXVCCB7PBmVlxdK6ma2NNaOM/c9jfQA8Gz7c7jAhgxmOq9aLCZR+OS SSAngReK5YW5k3DmLuFK3u/WKlnIbmU0fZ0zgAbCIzMnRW7xXCvyi58GPmJA2EddUg kdu0kFnNsMxML4MkkwPRkAavynVuovc8zowifNmI= From: Titus Manea Content-Type: multipart/alternative; boundary="Apple-Mail=_15343C98-1998-4DE2-BCA1-E5E6CED3734E" List-Id: Porting FreeBSD to ARM processors List-Archive: https://lists.freebsd.org/archives/freebsd-arm List-Help: List-Post: List-Subscribe: List-Unsubscribe: Sender: owner-freebsd-arm@FreeBSD.org Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3826.700.81\)) Subject: allwinner gpio bank offset Message-Id: <83D87B14-084B-4780-9ECC-DE64559FD736@edc.ro> Date: Tue, 25 Nov 2025 14:12:06 +0200 To: freebsd-arm X-Mailer: Apple Mail (2.3826.700.81) X-Spam-Level: * X-Spam-Checker-Version: SpamAssassin 4.0.0 (2022-12-14) on ns.edc.ro X-Spamd-Bar: --- X-Spamd-Result: default: False [-3.50 / 15.00]; NEURAL_HAM_MEDIUM(-1.00)[-1.000]; NEURAL_HAM_LONG(-1.00)[-1.000]; NEURAL_HAM_SHORT(-1.00)[-1.000]; R_DKIM_ALLOW(-0.20)[edc.ro:s=mail]; R_SPF_ALLOW(-0.20)[+mx]; MIME_GOOD(-0.10)[multipart/alternative,text/plain]; DMARC_NA(0.00)[edc.ro]; RCPT_COUNT_ONE(0.00)[1]; ASN(0.00)[asn:8708, ipnet:86.120.0.0/13, country:RO]; RCVD_VIA_SMTP_AUTH(0.00)[]; MIME_TRACE(0.00)[0:+,1:+,2:~]; APPLE_MAILER_COMMON(0.00)[]; RCVD_TLS_ALL(0.00)[]; MID_RHS_MATCH_FROM(0.00)[]; RCVD_COUNT_TWO(0.00)[2]; FROM_EQ_ENVFROM(0.00)[]; FROM_HAS_DN(0.00)[]; ARC_NA(0.00)[]; TO_MATCH_ENVRCPT_ALL(0.00)[]; TO_DN_ALL(0.00)[]; PREVIOUSLY_DELIVERED(0.00)[freebsd-arm@freebsd.org]; MLMMJ_DEST(0.00)[freebsd-arm@freebsd.org]; DKIM_TRACE(0.00)[edc.ro:+] X-Rspamd-Queue-Id: 4dG1lw3gfcz4KHM --Apple-Mail=_15343C98-1998-4DE2-BCA1-E5E6CED3734E Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=us-ascii The Allwinner pincontroller register layout used to allow for at least 11 banks per controller, any more banks would reside at a second controller instance. When the per-bank register map size was increased with the D1, it turned out that the last bank (port K) of those maximum 11 banks actually would not fit anymore in the 512 bytes reserved for the pincontroller = registers. On new SoCs Allwinner thus moved the last bank beyond the existing registers, at offset 0x500. So far SoCs never used more than 9 banks per controller, but the new Allwinner A523 actually uses all 11 banks. Since that SoC also uses the extended layout, its PortK needs to be programmed at offset 0x500. Factor out the bank offset calculation into a new function, and handle the case for the last bank separately. Since none of the older SoCs ever used PortK, we can ignore this case, and just always use offset 0x500 for the last bank. source = https://patchew.org/linux/20250306235827.4895-1-andre.przywara@arm.com/202= 50306235827.4895-4-andre.przywara@arm.com/ so we need to change the AW_GPIO_GP_BASE macro #define AW_BASE_1(_sc, _bank, _o) ((_sc)->conf->bank_size * = (_bank) + (_o)) #define BANK_K ('K' - 'A') #define IS_BANK_K(_sc, _bank) (AW_BASE_1(_sc, _bank, 0) > = 0x200) #define AW_GPIO_GP_BASE(_sc, _bank) (IS_BANK_K(_sc, _bank) ? \ AW_BASE_1((_sc), ((_bank) - = BANK_K), 0x500) : \ AW_BASE_1((_sc), (_bank), 0)) --Apple-Mail=_15343C98-1998-4DE2-BCA1-E5E6CED3734E Content-Transfer-Encoding: quoted-printable Content-Type: text/html; charset=us-ascii The Allwinner pincontroller register = layout used to allow for at least 11 banks per controller, any more banks would reside at a second controller instance. When the per-bank register map size was increased with the D1, it turned out that the last bank (port K) of those maximum 11 banks actually would not fit anymore in the 512 bytes reserved for the pincontroller = registers. On new SoCs Allwinner thus moved the last bank beyond the existing registers, at offset 0x500. So far SoCs never used more than 9 banks per controller, but the new Allwinner A523 actually uses all 11 banks. Since that SoC also uses the extended layout, its PortK needs to be programmed at offset 0x500. Factor out the bank offset calculation into a new function, and handle the case for the last bank separately. Since none of the older SoCs ever used PortK, we can ignore this case, and just always use offset 0x500 for the last bank.
source
so
we need to = change the AW_GPIO_GP_BASE = macro

#define = AW_BASE_1(_sc, _bank, _o)       = ((_sc)->conf->bank_size * (_bank) + (_o))

#define BANK_K               =            ('K' - = 'A')
#define IS_BANK_K(_sc, = _bank)           (AW_BASE_1(_sc, _bank, 0) > = 0x200)
#define = AW_GPIO_GP_BASE(_sc, _bank)     (IS_BANK_K(_sc, _bank) ? = \
      =                     =                 =  AW_BASE_1((_sc), ((_bank) - BANK_K), 0x500) : = \
      =                     =                 =  AW_BASE_1((_sc), (_bank), = 0))

= --Apple-Mail=_15343C98-1998-4DE2-BCA1-E5E6CED3734E--