From owner-svn-soc-all@FreeBSD.ORG Sat Sep 7 16:09:44 2013 Return-Path: Delivered-To: svn-soc-all@FreeBSD.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id 8A033AEA for ; Sat, 7 Sep 2013 16:09:44 +0000 (UTC) (envelope-from zcore@FreeBSD.org) Received: from socsvn.freebsd.org (socsvn.freebsd.org [IPv6:2001:1900:2254:206a::50:2]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 76B6F2811 for ; Sat, 7 Sep 2013 16:09:44 +0000 (UTC) Received: from socsvn.freebsd.org ([127.0.1.124]) by socsvn.freebsd.org (8.14.7/8.14.7) with ESMTP id r87G9iCW022504 for ; Sat, 7 Sep 2013 16:09:44 GMT (envelope-from zcore@FreeBSD.org) Received: (from www@localhost) by socsvn.freebsd.org (8.14.7/8.14.6/Submit) id r87G9iXp022496 for svn-soc-all@FreeBSD.org; Sat, 7 Sep 2013 16:09:44 GMT (envelope-from zcore@FreeBSD.org) Date: Sat, 7 Sep 2013 16:09:44 GMT Message-Id: <201309071609.r87G9iXp022496@socsvn.freebsd.org> X-Authentication-Warning: socsvn.freebsd.org: www set sender to zcore@FreeBSD.org using -f From: zcore@FreeBSD.org To: svn-soc-all@FreeBSD.org Subject: socsvn commit: r257085 - soc2013/zcore/head/usr.sbin/bhyve MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-soc-all@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: SVN commit messages for the entire Summer of Code repository List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 07 Sep 2013 16:09:44 -0000 Author: zcore Date: Sat Sep 7 16:09:44 2013 New Revision: 257085 URL: http://svnweb.FreeBSD.org/socsvn/?view=rev&rev=257085 Log: support ATA_READ_FPDMA_QUEUED and ATA_WRITE_FPDMA_QUEUED Modified: soc2013/zcore/head/usr.sbin/bhyve/block_if.c soc2013/zcore/head/usr.sbin/bhyve/pci_ahci.c Modified: soc2013/zcore/head/usr.sbin/bhyve/block_if.c ============================================================================== --- soc2013/zcore/head/usr.sbin/bhyve/block_if.c Sat Sep 7 16:08:48 2013 (r257084) +++ soc2013/zcore/head/usr.sbin/bhyve/block_if.c Sat Sep 7 16:09:44 2013 (r257085) @@ -49,7 +49,7 @@ #define BLOCKIF_SIG 0xb109b109 -#define BLOCKIF_MAXREQ 8 +#define BLOCKIF_MAXREQ 32 enum blockop { BOP_READ, Modified: soc2013/zcore/head/usr.sbin/bhyve/pci_ahci.c ============================================================================== --- soc2013/zcore/head/usr.sbin/bhyve/pci_ahci.c Sat Sep 7 16:08:48 2013 (r257084) +++ soc2013/zcore/head/usr.sbin/bhyve/pci_ahci.c Sat Sep 7 16:09:44 2013 (r257085) @@ -177,7 +177,6 @@ sc->is |= (1 << i); } - dprintf("%x %x\n", sc->port[0].is, sc->port[0].ie); DPRINTF(("%s %x\n", __func__, sc->is)); if (sc->is && (sc->ghc & AHCI_GHC_IE)) pci_generate_msi(sc->asc_pi, 0); @@ -218,6 +217,24 @@ } } +static void ahci_write_fis_sdb(struct ahci_port *p, int slot, + uint32_t tfd) +{ + uint8_t fis[8]; + uint8_t error; + + error = (tfd >> 8) & 0xff; + memset(fis, 0, sizeof(fis)); + fis[0] = error; + fis[2] = tfd & 0x77; + *(uint32_t *)(fis + 4) = (1 << slot); + if (error & ATA_S_ERROR) + p->is |= AHCI_P_IX_TFE; + p->tfd = tfd; + p->ci &= ~(1 << slot); + ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis); +} + static void ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd) { @@ -328,7 +345,8 @@ struct ahci_prdt_entry *prdt = (struct ahci_prdt_entry *)(cfis + 0x80); struct ahci_cmd_hdr *hdr = p->cmd_lst + slot * AHCI_CL_SIZE; - if (cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48) + if (cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 || + cfis[2] == ATA_WRITE_FPDMA_QUEUED) readop = 0; if (!p->iofree) { @@ -339,24 +357,33 @@ return; } - if (cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) { + if (cfis[2] == ATA_WRITE_FPDMA_QUEUED || + cfis[2] == ATA_READ_FPDMA_QUEUED) { lba = ((uint64_t)cfis[10] << 40) | ((uint64_t)cfis[9] << 32) | ((uint64_t)cfis[8] << 24) | ((uint64_t)cfis[6] << 16) | ((uint64_t)cfis[5] << 8) | cfis[4]; - if (!cfis[12] && !cfis[13]) + len = cfis[11] << 8 | cfis[3]; + if (!len) + len = 65536; + } else if (cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) { + lba = ((uint64_t)cfis[10] << 40) | + ((uint64_t)cfis[9] << 32) | + ((uint64_t)cfis[8] << 24) | + ((uint64_t)cfis[6] << 16) | + ((uint64_t)cfis[5] << 8) | + cfis[4]; + len = cfis[13] << 8 | cfis[12]; + if (!len) len = 65536; - else - len = cfis[13] << 8 | cfis[12]; } else { lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) | (cfis[5] << 8) | cfis[4]; - if (!cfis[12]) + len = cfis[12]; + if (!len) len = 256; - else - len = cfis[12]; } lba *= blockif_sectsz(p->bctx); len *= blockif_sectsz(p->bctx); @@ -533,6 +560,8 @@ case ATA_WRITE_DMA: case ATA_READ_DMA48: case ATA_WRITE_DMA48: + case ATA_READ_FPDMA_QUEUED: + case ATA_WRITE_FPDMA_QUEUED: handle_dma(p, slot, cfis); break; case ATA_FLUSHCACHE: @@ -621,23 +650,38 @@ struct ahci_ioreq *aior; uint32_t tfd; struct ahci_cmd_hdr *hdr; + int ncq = 0; + + DPRINTF(("ahci_ioreq_cb %d\n", err)); aior = br->br_param; p = aior->io_pr; sc = p->pr_sc; hdr = p->cmd_lst + aior->slot * AHCI_CL_SIZE; + if (aior->cfis[2] == ATA_WRITE_FPDMA_QUEUED || + aior->cfis[2] == ATA_READ_FPDMA_QUEUED) + ncq = 1; - DPRINTF(("ahci_ioreq_cb %d\n", err)); pthread_mutex_lock(&sc->mtx); if (!err) { tfd = ATA_S_READY | ATA_S_DSC; - hdr->prdbc = aior->len; + if (ncq) + hdr->prdbc = 0; + else + hdr->prdbc = aior->len; } else { tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR; hdr->prdbc = 0; + if (ncq) + p->serr |= (1 << aior->slot); } - ahci_write_fis_d2h(p, aior->slot, aior->cfis, tfd); + + if (ncq) { + p->sact &= ~(1 << aior->slot); + ahci_write_fis_sdb(p, aior->slot, tfd); + } else + ahci_write_fis_d2h(p, aior->slot, aior->cfis, tfd); /* * Move the blockif request back to the free list