From owner-freebsd-arm@FreeBSD.ORG Mon May 5 23:40:53 2014 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTPS id C6BF26D2 for ; Mon, 5 May 2014 23:40:53 +0000 (UTC) Received: from feith1.FEITH.COM (feith1.FEITH.COM [192.251.93.1]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 8D41C1FD for ; Mon, 5 May 2014 23:40:53 +0000 (UTC) Received: from jwlab.FEITH.COM (jwlab.FEITH.COM [192.251.93.16]) by feith1.FEITH.COM (8.14.5+Sun/8.12.9) with ESMTP id s45Nem5p027279; Mon, 5 May 2014 19:40:48 -0400 (EDT) (envelope-from john@jwlab.FEITH.COM) Received: from jwlab.FEITH.COM (localhost [127.0.0.1]) by jwlab.FEITH.COM (8.14.5+Sun/8.14.5) with ESMTP id s45Nemxm015291; Mon, 5 May 2014 19:40:48 -0400 (EDT) Received: (from john@localhost) by jwlab.FEITH.COM (8.14.5+Sun/8.14.5/Submit) id s45Nem4o015290; Mon, 5 May 2014 19:40:48 -0400 (EDT) Date: Mon, 5 May 2014 19:40:48 -0400 (EDT) From: John Wehle Message-Id: <201405052340.s45Nem4o015290@jwlab.FEITH.COM> To: fun@naobsd.org Subject: Re: Amlogic aml8726-m3 / aml8726-m6 SoC status MIME-Version: 1.0 Content-Type: text/plain X-DCC--Metrics: feith1; whitelist X-Scanned-By: MIMEDefang 2.67 on 192.251.93.1 Cc: freebsd-arm@freebsd.org X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: "Porting FreeBSD to ARM processors." List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 05 May 2014 23:40:53 -0000 > I have a aml8726-m1 box and a aml8726-m1 tablet. do you have any > information about m1? Some. I do not have / plan on testing on aml8726-m1, however others are certainly welcomed to give it a go. Much of the code I've implemented should also work for the aml8726-m1. In some cases (e.g. the RTC driver) I've included additional configuration flexibility which should support the m1, in other cases (e.g. the UART driver) no additional effort appeared necessary. I'll note that the USB phy changed a bit between the m1 and the later chips ... the current code doesn't attempt to accommodate the m1 flavor (though it's probably easy enough to add the necessary support). -- John ------------------------------------------------------------------------- | Feith Systems | Voice: 1-215-646-8000 | Email: john@feith.com | | John Wehle | Fax: 1-215-540-5495 | | -------------------------------------------------------------------------