Date: Wed, 3 Aug 2016 18:27:28 +0200 From: Bernd Walter <ticso@cicely7.cicely.de> To: FreeBSD-arm@freebsd.org Cc: Bernd Walter <ticso@cicely7.cicely.de> Subject: Re: SPI on Raspberry B+ Message-ID: <20160803162728.GE18406@cicely7.cicely.de> In-Reply-To: <20160803034851.GC18406@cicely7.cicely.de> References: <20160803032830.GB18406@cicely7.cicely.de> <20160803034851.GC18406@cicely7.cicely.de>
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On Wed, Aug 03, 2016 at 05:48:51AM +0200, Bernd Walter wrote: > On Wed, Aug 03, 2016 at 05:28:30AM +0200, Bernd Walter wrote: > > I'm currently writing a kernel driver for APA102 LEDs on 11-BETA3. > > With some help of older threads on this list I've managed to > > get my driver attached and sending data. > > However, what I didn't manged yet is setting the SPI parameters. > > > > The SPI mode seems to match fine. > > > > The byte order is unfortunately wrong. > > I need MSB first and the driver is sending LSB first. > > Of course I could rotate all the bits, but would like to avoid it > > for performance reasons. > > > > The clock is only 500kHz according to scope. > > I've heared that there is no device specific speed support, but since I'm > > not using any other SPI device setting the global speed would be fine. > > I've found out about sysctl dev.spi.0.clock. > That works fine. > > > I'm calling SPIBUS_TRANSFER with multiple bytes. > > There is a gap of 2 microseconds between the bytes. > > Don't know if it just skipping a full clock cycle and the gap will > > be shorter with a higher clockrate, or if the driver really needs > > 2 full microseconds between each bytes. > > I somehow believe (and hope) it is just a full cycle in the controller. > > It also remains at one clock cycle gap, so with higher speed the > gap will be shorter as well. > > Unfortunately there is no byteorder sysctl. Oh - stupid me. I've left some test pattern in my testcode. The drivers byteorder is in fact MSB first. -- B.Walter <bernd@bwct.de> http://www.bwct.de Modbus/TCP Ethernet I/O Baugruppen, ARM basierte FreeBSD Rechner uvm.
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