Date: Wed, 29 Dec 2010 02:38:05 +0800 (SGT) From: Darmawan Salihun <darmawan_salihun@yahoo.com> To: freebsd-hackers@freebsd.org, John Baldwin <jhb@freebsd.org> Subject: Re: PCI IDE Controller Base Address Register setting Message-ID: <551460.9153.qm@web76806.mail.sg1.yahoo.com> In-Reply-To: <201012281020.11953.jhb@freebsd.org>
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Hi,=0A=0A--- On Tue, 12/28/10, John Baldwin <jhb@freebsd.org> wrote:=0A=0A>=
From: John Baldwin <jhb@freebsd.org>=0A> Subject: Re: PCI IDE Controller B=
ase Address Register setting=0A> To: freebsd-hackers@freebsd.org=0A> Cc: "D=
armawan Salihun" <darmawan_salihun@yahoo.com>=0A> Date: Tuesday, December 2=
8, 2010, 10:20 AM=0A> On Monday, December 27, 2010 6:07:35=0A> am Darmawan =
Salihun wrote:=0A> > Hi, =0A> > =0A> > I'm trying to install FreeBSD 8.0 on=
AMD Geode LX800=0A> (CS5536 "southbridge"). =0A> However, it cannot detect=
the IDE controller (in the=0A> CS5536) correctly. It =0A> says something s=
imilar to this: =0A> > "IDE controller not present"=0A> =0A> Hmm, I can't f=
ind a message like that anywhere.=A0 Can=0A> you get the exact message =0A>=
you are seeing?=0A> =0A=0AIt says: =0A=0A"No disks found! Please verify th=
at your disk controller is being properly probed at boot time."=0A=0AThis h=
appens as I try to run fdisk during installation. The IDE HDD is on the pri=
mary slave because the primary master is a CF slot.=0AMoreover, the integra=
ted IDE controller only has support for =0A__single__ IDE channel, the prim=
ary IDE channel.=0A=0A=0A> > I did lspci in Linux (BackTrack 3) =0A> > and =
I saw that the IDE controller Base Address=0A> Registers (BARs) =0A> > are =
all disabled (only contains zeros), =0A> > except for one of them (BAR4). =
=0A> > BAR4 decodes 16-bytes I/O ports (FFF0h-FFFFh). =0A> > The decoded po=
rts "seems" to conform to the PCI IDE=0A> specification =0A> > for "native-=
PCI IDE controller" (relocatable within=0A> the =0A> > 16-bit I/O address s=
pace). =0A> > =0A> > I did "cat /proc/ioports" and I found that =0A> > the =
following I/O port address ranges decoded=0A> correctly =0A> > to the IDE c=
ontroller in the CS5536 "southbridge":=0A> > =0A> > 1F0h-1F7h =0A> > 3F6h =
=0A> > 170h-177h=0A> > FFF0h-FFFFh=0A> > =0A> > My question: =0A> > Does Fr=
eeBSD require the IDE controller BARs =0A> > to be programmed to also decod=
e =0A> > legacy I/O ports ranges (1F0h-1F7h,3F6h and=0A> 170h-177h)? =0A> =
=0A> No.=A0 We hardcode the ISA ranges for BARs 0 through 3=0A> if a PCI ID=
E controller =0A> has the "Primary" or "Secondary" bits set in its=0A> prog=
ramming interface =0A> register and don't even look at the BARs.=A0 =0A=0AP=
robably, the current setting in the PCI configuration =0Aspace of the IDE c=
ontroller contains some error in the =0Aprogramming interface register. I'l=
l re-probe with lspci =0Aand report back. =0A=0A> We do=0A> always examines=
BARs 4 and 5 =0A> using the normal probing scheme of writing all 1's,=0A> =
etc.=A0 The code in question =0A> looks like this:=0A> =0A> /*=0A> * For A=
TA devices we need to decide early what addressing=0A> mode to use.=0A> * =
Legacy demands that the primary and secondary ATA ports=0A> sits on the=0A>=
* same addresses that old ISA hardware did. This dictates=0A> that we use=
=0A> * those addresses and ignore the BAR's if we cannot set=0A> PCI nativ=
e=0A> * addressing mode.=0A> */=0A> static void=0A> pci_ata_maps(device_t=
bus, device_t dev, struct=0A> resource_list *rl, int force,=0A> =A0 =A0 ui=
nt32_t prefetchmask)=0A> {=0A> =A0=A0=A0 struct resource *r;=0A> =A0=A0=A0 =
int rid, type, progif;=0A> #if 0=0A> =A0=A0=A0 /* if this device supports P=
CI native=0A> addressing use it */=0A> =A0=A0=A0 progif =3D pci_read_config=
(dev,=0A> PCIR_PROGIF, 1);=0A> =A0=A0=A0 if ((progif & 0x8a) =3D=3D 0x8a) {=
=0A> =A0=A0=A0 =A0=A0=A0 if=0A> (pci_mapbase(pci_read_config(dev, PCIR_BAR(=
0), 4))=0A> &&=0A> =A0=A0=A0 =A0=A0=A0 =A0 =A0=0A> pci_mapbase(pci_read_con=
fig(dev, PCIR_BAR(2), 4))) {=0A> =A0=A0=A0 =A0=A0=A0 =A0=A0=A0=0A> printf("=
Trying ATA native PCI addressing mode\n");=0A> =A0=A0=A0 =A0=A0=A0 =A0=A0=
=A0=0A> pci_write_config(dev, PCIR_PROGIF, progif | 0x05, 1);=0A> =A0=A0=A0=
=A0=A0=A0 }=0A> =A0=A0=A0 }=0A> #endif=0A> =A0=A0=A0 progif =3D pci_read_c=
onfig(dev,=0A> PCIR_PROGIF, 1);=0A> =A0=A0=A0 type =3D SYS_RES_IOPORT;=0A> =
=A0=A0=A0 if (progif &=0A> PCIP_STORAGE_IDE_MODEPRIM) {=0A> =A0=A0=A0 =A0=
=A0=A0 pci_add_map(bus, dev,=0A> PCIR_BAR(0), rl, force,=0A> =A0=A0=A0 =A0=
=A0=A0 =A0 =A0=0A> prefetchmask & (1 << 0));=0A> =A0=A0=A0 =A0=A0=A0 pci_ad=
d_map(bus, dev,=0A> PCIR_BAR(1), rl, force,=0A> =A0=A0=A0 =A0=A0=A0 =A0 =A0=
=0A> prefetchmask & (1 << 1));=0A> =A0=A0=A0 } else {=0A> =A0=A0=A0 =A0=A0=
=A0 rid =3D PCIR_BAR(0);=0A> =A0=A0=A0 =A0=A0=A0 resource_list_add(rl,=0A> =
type, rid, 0x1f0, 0x1f7, 8);=0A> =A0=A0=A0 =A0=A0=A0 r =3D=0A> resource_lis=
t_reserve(rl, bus, dev, type, &rid, 0x1f0,=0A> =A0=A0=A0 =A0=A0=A0 =A0 =A0 =
0x1f7,=0A> 8, 0);=0A> =A0=A0=A0 =A0=A0=A0 rid =3D PCIR_BAR(1);=0A> =A0=A0=
=A0 =A0=A0=A0 resource_list_add(rl,=0A> type, rid, 0x3f6, 0x3f6, 1);=0A> =
=A0=A0=A0 =A0=A0=A0 r =3D=0A> resource_list_reserve(rl, bus, dev, type, &ri=
d, 0x3f6,=0A> =A0=A0=A0 =A0=A0=A0 =A0 =A0 0x3f6,=0A> 1, 0);=0A> =A0=A0=A0 }=
=0A> =A0=A0=A0 if (progif &=0A> PCIP_STORAGE_IDE_MODESEC) {=0A> =A0=A0=A0 =
=A0=A0=A0 pci_add_map(bus, dev,=0A> PCIR_BAR(2), rl, force,=0A> =A0=A0=A0 =
=A0=A0=A0 =A0 =A0=0A> prefetchmask & (1 << 2));=0A> =A0=A0=A0 =A0=A0=A0 pci=
_add_map(bus, dev,=0A> PCIR_BAR(3), rl, force,=0A> =A0=A0=A0 =A0=A0=A0 =A0 =
=A0=0A> prefetchmask & (1 << 3));=0A> =A0=A0=A0 } else {=0A> =A0=A0=A0 =A0=
=A0=A0 rid =3D PCIR_BAR(2);=0A> =A0=A0=A0 =A0=A0=A0 resource_list_add(rl,=
=0A> type, rid, 0x170, 0x177, 8);=0A> =A0=A0=A0 =A0=A0=A0 r =3D=0A> resourc=
e_list_reserve(rl, bus, dev, type, &rid, 0x170,=0A> =A0=A0=A0 =A0=A0=A0 =A0=
=A0 0x177,=0A> 8, 0);=0A> =A0=A0=A0 =A0=A0=A0 rid =3D PCIR_BAR(3);=0A> =A0=
=A0=A0 =A0=A0=A0 resource_list_add(rl,=0A> type, rid, 0x376, 0x376, 1);=0A>=
=A0=A0=A0 =A0=A0=A0 r =3D=0A> resource_list_reserve(rl, bus, dev, type, &r=
id, 0x376,=0A> =A0=A0=A0 =A0=A0=A0 =A0 =A0 0x376,=0A> 1, 0);=0A> =A0=A0=A0 =
}=0A> =A0=A0=A0 pci_add_map(bus, dev, PCIR_BAR(4), rl,=0A> force,=0A> =A0=
=A0=A0 =A0 =A0 prefetchmask & (1=0A> << 4));=0A> =A0=A0=A0 pci_add_map(bus,=
dev, PCIR_BAR(5), rl,=0A> force,=0A> =A0=A0=A0 =A0 =A0 prefetchmask & (1=
=0A> << 5));=0A> }=0A> =0A> =0A=0AThanks for the hints. =0A=0A-Darmawan=0A=
=0A> -- =0A> John Baldwin=0A> _____________________________________________=
__=0A> freebsd-hackers@freebsd.org=0A> mailing list=0A> http://lists.freebs=
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