From owner-freebsd-hackers Sun Aug 3 02:24:20 1997 Return-Path: Received: (from root@localhost) by hub.freebsd.org (8.8.5/8.8.5) id CAA15868 for hackers-outgoing; Sun, 3 Aug 1997 02:24:20 -0700 (PDT) Received: from bugs.us.dell.com (bugs.us.dell.com [143.166.169.147]) by hub.freebsd.org (8.8.5/8.8.5) with SMTP id CAA15863 for ; Sun, 3 Aug 1997 02:24:17 -0700 (PDT) Received: from ant.us.dell.com (ant.us.dell.com [198.64.66.34]) by bugs.us.dell.com (8.6.12/8.6.12) with SMTP id EAA02546; Sun, 3 Aug 1997 04:21:59 -0500 Message-Id: <3.0.2.32.19970803041901.006a69e4@bugs.us.dell.com> X-Sender: tony@bugs.us.dell.com X-Mailer: QUALCOMM Windows Eudora Light Version 3.0.2 (32) Date: Sun, 03 Aug 1997 04:19:01 -0500 To: Terry Lambert From: Tony Overfield Subject: Re: Pentium II? Cc: hackers@FreeBSD.ORG In-Reply-To: <199708022310.QAA00461@phaeton.artisoft.com> References: <3.0.2.32.19970802023853.0069c4c4@bugs.us.dell.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Sender: owner-freebsd-hackers@FreeBSD.ORG X-Loop: FreeBSD.org Precedence: bulk At 04:10 PM 8/2/97 -0700, Terry Lambert wrote: >You guys didn't call them that, but the memory bus was running at 33MHz; >that's "clock doubled" in my book. > >I have a friend who had one until the Pentium math bugs reared their >ugly heads (he was an IDE weenie, so he didn't care that PCI bus >mastering failed on the thing). Can you remember a specific model number? If so, I can reach up onto my shelf and pull one of them down and measure it. I doubt it, but maybe I measured it wrong the first time around. >> Due to that bug, that version of the Saturn chipset does not support >> write-back L2 caching and it is therefore configured by the BIOS to >> use the L2 cache in write-through mode, though the L1 cache is always >> write-back. The missing trace is not used or needed when the L2 >> cache is in write-through mode. > >Unless a DMA initiated by a controller rather than the host occurs. >Check the -hackers list archives for postings on disabling the L1 >and L2 cache on these monstrosities... I tried searching -hackers ("Dell AND disabl* AND cach*") and only found one claim (yours, BTW) that this bug exists. Interestingly, the only reply seemed to disagree with your claim. Perhaps you can offer some better search keywords. >Maybe not; maybe the memory was just jumpered for an extra wait state; >whatever; memory access was half as fast as it should have been in a >reasonable implementation. Well, that's quite a bit different, but still apparently wrong. It is true that the very first Pentium-60 systems had a write-through L2 cache which makes memory writes appear slower, but it also eliminates the DMA problem you mentioned. >> >Just as my 486/50 kicks butt over the same chips. >> >> I doubt this, unless you're "stacking the deck" in some perverse >> way, or you're simply dreaming. > >Of course I am, if an I/O intensive benchmark is "stacking the deck" >and a CPU intensive benchmark is somehow "a good idea". I have no problem with I/O intensive benchmarks, but improperly interpreting the results and factoring in bogus assumptions should be avoided, if possible. Don't forget than Pentium memory is 64 bits wide and 486/50 memory is 32 bits wide. Thus, your fancy 486/50 memory bus cannot help to explain your faster I/O claims, so maybe you've got a "magic I/O bus." >I'm doing disk I/O, of course, and I am overclocking the EISA bus on >the machine to 50MHz instead of 2x25. 50MHz EISA transfers data faster >than 30MHz PCI... or 33MHz. Wow! You do have a magic bus. Do you expect me to believe that you run your EISA bus at 600% of the maximum speed of 8.33 MHz!!!??? There's never been an EISA bus that is faster than a PCI bus. >8-). Oh, I see, you're just kidding.... ;-) - Tony