Date: Fri, 13 Sep 1996 09:12:12 -0700 (PDT) From: "Rodney W. Grimes" <rgrimes@GndRsh.aac.dev.com> To: jmb@freefall.freebsd.org (Jonathan M. Bresler) Cc: michaelh@cet.co.jp, mrcpu@cdsnet.net, jhs@freebsd.org, sysseh@devetir.qld.gov.au, current@freebsd.org Subject: Re: VM/kernel problems? Message-ID: <199609131612.JAA00510@GndRsh.aac.dev.com> In-Reply-To: <199609131507.IAA26035@freefall.freebsd.org> from "Jonathan M. Bresler" at "Sep 13, 96 08:07:30 am"
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> Michael Hancock wrote: > > > > On Thu, 12 Sep 1996, Jaye Mathisen wrote: > > > > > > > > Hmmm, as of -current supped on the 11th and 12th, my box is working just > > > yippee skippee after a make world. > > > > > > Although I'm not using John's cache color mumbo-jumbo voodoo > > > evilness. > > > > It's really not voodoo, it's about better distribution of addresses in the > > cache. You can do this by using some spare space to vary the offsets into > > actively used chunks of memory. > > page coloring improves the cache hit ratio. it is "A Good Thing (TM)" > see curt schimmel's _unix_systems_for_modern_architecture_ > pg 137 section 7.2.3 Physically Indexed Caches > > now only if we could dynamically determine the cache size and > set the configuration of the coloring code to match >;) If John can fix the code up to take a variable set during the PCI chipset probe code I can give him the physical cache size for the Triton, Triton II (HX and VX), Natoma and Orion chipsets. (I think I can get the Pentium PRO independent of chipset, but not quite sure yet.) The default value could still be 64K incase none of the cache sizeable chipsets are found, but in my experience the only things that ever had 64K or 128K caches on them are old 386 boards and some of the earlier 486 boards. Thus if CPU >= I586 your going to have a 256K cache.... -- Rod Grimes rgrimes@gndrsh.aac.dev.com Accurate Automation Company Reliable computers for FreeBSD
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