Date: Tue, 26 Sep 2006 13:40:13 GMT From: Attilio Rao <attilio@FreeBSD.org> To: Perforce Change Reviews <perforce@FreeBSD.org> Subject: PERFORCE change 106721 for review Message-ID: <200609261340.k8QDeDvD032523@repoman.freebsd.org>
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http://perforce.freebsd.org/chv.cgi?CH=106721 Change 106721 by attilio@attilio_laptop on 2006/09/26 13:39:51 Make some modifies I missed Affected files ... .. //depot/projects/usb/src/sys/dev/usb/if_auereg.h#8 edit .. //depot/projects/usb/src/sys/dev/usb/if_axereg.h#8 edit Differences ... ==== //depot/projects/usb/src/sys/dev/usb/if_auereg.h#8 (text+ko) ==== @@ -42,134 +42,144 @@ * are 8 bits wide. * * Packet transfer is done in 64 byte chunks. The last chunk in a - * transfer is denoted by having a length less that 64 bytes. For + * transfer is denoted by having a length less that 64 bytes. For * the RX case, the data includes an optional RX status word. */ -#define AUE_UR_READREG 0xF0 -#define AUE_UR_WRITEREG 0xF1 +#define AUE_UR_READREG 0xF0 +#define AUE_UR_WRITEREG 0xF1 -#define AUE_CONFIG_NO 1 -#define AUE_IFACE_IDX 0 +#define AUE_CONFIG_NO 1 +#define AUE_IFACE_IDX 0 /* - * Note that while the ADMtek technically has four - * endpoints, the control endpoint (endpoint 0) is - * regarded as special by the USB code and drivers - * don't have direct access to it. (We access it - * using usbd_do_request() when reading/writing - * registers.) Consequently, our endpoint indexes - * don't match those in the ADMtek Pegasus manual: - * we consider the RX data endpoint to be index 0 - * and work up from there. + * Note that while the ADMtek technically has four endpoints, the control + * endpoint (endpoint 0) is regarded as special by the USB code and drivers + * don't have direct access to it (we access it using usbd_do_request() + * when reading/writing registers. Consequently, our endpoint indexes + * don't match those in the ADMtek Pegasus manual: we consider the RX data + * endpoint to be index 0 and work up from there. */ -#define AUE_ENDPT_MAX 6 +#define AUE_ENDPT_MAX 6 + +#define AUE_INTR_PKTLEN 0x8 + +#define AUE_CTL0 0x00 +#define AUE_CTL1 0x01 +#define AUE_CTL2 0x02 +#define AUE_MAR0 0x08 +#define AUE_MAR1 0x09 +#define AUE_MAR2 0x0A +#define AUE_MAR3 0x0B +#define AUE_MAR4 0x0C +#define AUE_MAR5 0x0D +#define AUE_MAR6 0x0E +#define AUE_MAR7 0x0F +#define AUE_MAR AUE_MAR0 +#define AUE_PAR0 0x10 +#define AUE_PAR1 0x11 +#define AUE_PAR2 0x12 +#define AUE_PAR3 0x13 +#define AUE_PAR4 0x14 +#define AUE_PAR5 0x15 +#define AUE_PAR AUE_PAR0 +#define AUE_PAUSE0 0x18 +#define AUE_PAUSE1 0x19 +#define AUE_PAUSE AUE_PAUSE0 +#define AUE_RX_FLOWCTL_CNT 0x1A +#define AUE_RX_FLOWCTL_FIFO 0x1B +#define AUE_REG_1D 0x1D +#define AUE_EE_REG 0x20 +#define AUE_EE_DATA0 0x21 +#define AUE_EE_DATA1 0x22 +#define AUE_EE_DATA AUE_EE_DATA0 +#define AUE_EE_CTL 0x23 +#define AUE_PHY_ADDR 0x25 +#define AUE_PHY_DATA0 0x26 +#define AUE_PHY_DATA1 0x27 +#define AUE_PHY_DATA AUE_PHY_DATA0 +#define AUE_PHY_CTL 0x28 +#define AUE_USB_STS 0x2A +#define AUE_TXSTAT0 0x2B +#define AUE_TXSTAT1 0x2C +#define AUE_TXSTAT AUE_TXSTAT0 +#define AUE_RXSTAT 0x2D +#define AUE_PKTLOST0 0x2E +#define AUE_PKTLOST1 0x2F +#define AUE_PKTLOST AUE_PKTLOST0 + +#define AUE_REG_7B 0x7B +#define AUE_GPIO0 0x7E +#define AUE_GPIO1 0x7F +#define AUE_REG_81 0x81 -#define AUE_INTR_PKTLEN 0x8 +#define AUE_CTL0_INCLUDE_RXCRC 0x01 +#define AUE_CTL0_ALLMULTI 0x02 +#define AUE_CTL0_STOP_BACKOFF 0x04 +#define AUE_CTL0_RXSTAT_APPEND 0x08 +#define AUE_CTL0_WAKEON_ENB 0x10 +#define AUE_CTL0_RXPAUSE_ENB 0x20 +#define AUE_CTL0_RX_ENB 0x40 +#define AUE_CTL0_TX_ENB 0x80 -#define AUE_CTL0 0x00 -#define AUE_CTL1 0x01 -#define AUE_CTL2 0x02 -#define AUE_MAR0 0x08 -#define AUE_MAR1 0x09 -#define AUE_MAR2 0x0A -#define AUE_MAR3 0x0B -#define AUE_MAR4 0x0C -#define AUE_MAR5 0x0D -#define AUE_MAR6 0x0E -#define AUE_MAR7 0x0F -#define AUE_MAR AUE_MAR0 -#define AUE_PAR0 0x10 -#define AUE_PAR1 0x11 -#define AUE_PAR2 0x12 -#define AUE_PAR3 0x13 -#define AUE_PAR4 0x14 -#define AUE_PAR5 0x15 -#define AUE_PAR AUE_PAR0 -#define AUE_PAUSE0 0x18 -#define AUE_PAUSE1 0x19 -#define AUE_PAUSE AUE_PAUSE0 -#define AUE_RX_FLOWCTL_CNT 0x1A -#define AUE_RX_FLOWCTL_FIFO 0x1B -#define AUE_REG_1D 0x1D -#define AUE_EE_REG 0x20 -#define AUE_EE_DATA0 0x21 -#define AUE_EE_DATA1 0x22 -#define AUE_EE_DATA AUE_EE_DATA0 -#define AUE_EE_CTL 0x23 -#define AUE_PHY_ADDR 0x25 -#define AUE_PHY_DATA0 0x26 -#define AUE_PHY_DATA1 0x27 -#define AUE_PHY_DATA AUE_PHY_DATA0 -#define AUE_PHY_CTL 0x28 -#define AUE_USB_STS 0x2A -#define AUE_TXSTAT0 0x2B -#define AUE_TXSTAT1 0x2C -#define AUE_TXSTAT AUE_TXSTAT0 -#define AUE_RXSTAT 0x2D -#define AUE_PKTLOST0 0x2E -#define AUE_PKTLOST1 0x2F -#define AUE_PKTLOST AUE_PKTLOST0 +#define AUE_CTL1_HOMELAN 0x04 +#define AUE_CTL1_RESETMAC 0x08 +#define AUE_CTL1_SPEEDSEL 0x10 /* 0 = 10mbps, 1 = 100mbps */ +#define AUE_CTL1_DUPLEX 0x20 /* 0 = half, 1 = full */ +#define AUE_CTL1_DELAYHOME 0x40 -#define AUE_REG_7B 0x7B -#define AUE_GPIO0 0x7E -#define AUE_GPIO1 0x7F -#define AUE_REG_81 0x81 +#define AUE_CTL2_EP3_CLR 0x01 /* reading EP3 clrs status regs */ +#define AUE_CTL2_RX_BADFRAMES 0x02 +#define AUE_CTL2_RX_PROMISC 0x04 +#define AUE_CTL2_LOOPBACK 0x08 +#define AUE_CTL2_EEPROMWR_ENB 0x10 +#define AUE_CTL2_EEPROM_LOAD 0x20 -#define AUE_CTL0_INCLUDE_RXCRC 0x01 -#define AUE_CTL0_ALLMULTI 0x02 -#define AUE_CTL0_STOP_BACKOFF 0x04 -#define AUE_CTL0_RXSTAT_APPEND 0x08 -#define AUE_CTL0_WAKEON_ENB 0x10 -#define AUE_CTL0_RXPAUSE_ENB 0x20 -#define AUE_CTL0_RX_ENB 0x40 -#define AUE_CTL0_TX_ENB 0x80 +#define AUE_EECTL_WRITE 0x01 +#define AUE_EECTL_READ 0x02 +#define AUE_EECTL_DONE 0x04 -#define AUE_CTL1_HOMELAN 0x04 -#define AUE_CTL1_RESETMAC 0x08 -#define AUE_CTL1_SPEEDSEL 0x10 /* 0 = 10mbps, 1 = 100mbps */ -#define AUE_CTL1_DUPLEX 0x20 /* 0 = half, 1 = full */ -#define AUE_CTL1_DELAYHOME 0x40 +#define AUE_PHYCTL_PHYREG 0x1F +#define AUE_PHYCTL_WRITE 0x20 +#define AUE_PHYCTL_READ 0x40 +#define AUE_PHYCTL_DONE 0x80 -#define AUE_CTL2_EP3_CLR 0x01 /* reading EP3 clrs status regs */ -#define AUE_CTL2_RX_BADFRAMES 0x02 -#define AUE_CTL2_RX_PROMISC 0x04 -#define AUE_CTL2_LOOPBACK 0x08 -#define AUE_CTL2_EEPROMWR_ENB 0x10 -#define AUE_CTL2_EEPROM_LOAD 0x20 +#define AUE_USBSTS_SUSPEND 0x01 +#define AUE_USBSTS_RESUME 0x02 -#define AUE_EECTL_WRITE 0x01 -#define AUE_EECTL_READ 0x02 -#define AUE_EECTL_DONE 0x04 +#define AUE_TXSTAT0_JABTIMO 0x04 +#define AUE_TXSTAT0_CARLOSS 0x08 +#define AUE_TXSTAT0_NOCARRIER 0x10 +#define AUE_TXSTAT0_LATECOLL 0x20 +#define AUE_TXSTAT0_EXCESSCOLL 0x40 +#define AUE_TXSTAT0_UNDERRUN 0x80 -#define AUE_PHYCTL_PHYREG 0x1F -#define AUE_PHYCTL_WRITE 0x20 -#define AUE_PHYCTL_READ 0x40 -#define AUE_PHYCTL_DONE 0x80 +#define AUE_TXSTAT1_PKTCNT 0x0F +#define AUE_TXSTAT1_FIFO_EMPTY 0x40 +#define AUE_TXSTAT1_FIFO_FULL 0x80 -#define AUE_USBSTS_SUSPEND 0x01 -#define AUE_USBSTS_RESUME 0x02 +#define AUE_RXSTAT_OVERRUN 0x01 +#define AUE_RXSTAT_PAUSE 0x02 -#define AUE_TXSTAT0_JABTIMO 0x04 -#define AUE_TXSTAT0_CARLOSS 0x08 -#define AUE_TXSTAT0_NOCARRIER 0x10 -#define AUE_TXSTAT0_LATECOLL 0x20 -#define AUE_TXSTAT0_EXCESSCOLL 0x40 -#define AUE_TXSTAT0_UNDERRUN 0x80 +#define AUE_GPIO_IN0 0x01 +#define AUE_GPIO_OUT0 0x02 +#define AUE_GPIO_SEL0 0x04 +#define AUE_GPIO_IN1 0x08 +#define AUE_GPIO_OUT1 0x10 +#define AUE_GPIO_SEL1 0x20 -#define AUE_TXSTAT1_PKTCNT 0x0F -#define AUE_TXSTAT1_FIFO_EMPTY 0x40 -#define AUE_TXSTAT1_FIFO_FULL 0x80 +#define AUE_TIMEOUT 100 /* 10*ms */ +#define AUE_MIN_FRAMELEN 60 -#define AUE_RXSTAT_OVERRUN 0x01 -#define AUE_RXSTAT_PAUSE 0x02 +#define AUE_RXSTAT_MCAST 0x01 +#define AUE_RXSTAT_GIANT 0x02 +#define AUE_RXSTAT_RUNT 0x04 +#define AUE_RXSTAT_CRCERR 0x08 +#define AUE_RXSTAT_DRIBBLE 0x10 +#define AUE_RXSTAT_MASK 0x1E -#define AUE_GPIO_IN0 0x01 -#define AUE_GPIO_OUT0 0x02 -#define AUE_GPIO_SEL0 0x04 -#define AUE_GPIO_IN1 0x08 -#define AUE_GPIO_OUT1 0x10 -#define AUE_GPIO_SEL1 0x20 +#define GET_MII(sc) ((sc)->sc_miibus ? \ + device_get_softc((sc)->sc_miibus) : NULL) struct aue_intrpkt { uint8_t aue_txstat0; @@ -186,15 +196,6 @@ uint8_t aue_rxstat; } __packed; -#define AUE_RXSTAT_MCAST 0x01 -#define AUE_RXSTAT_GIANT 0x02 -#define AUE_RXSTAT_RUNT 0x04 -#define AUE_RXSTAT_CRCERR 0x08 -#define AUE_RXSTAT_DRIBBLE 0x10 -#define AUE_RXSTAT_MASK 0x1E - -#define GET_MII(sc) ((sc)->sc_miibus ? \ - device_get_softc((sc)->sc_miibus) : NULL) struct aue_softc { struct usbd_config_td sc_config_td; @@ -229,9 +230,6 @@ uint8_t sc_name[16]; }; -#define AUE_TIMEOUT 100 /* 10*ms */ -#define AUE_MIN_FRAMELEN 60 - struct aue_config_copy { uint32_t if_flags; uint8_t if_lladdr[ETHER_ADDR_LEN]; ==== //depot/projects/usb/src/sys/dev/usb/if_axereg.h#8 (text+ko) ====
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