From owner-svn-src-head@freebsd.org Tue Jun 13 12:07:20 2017 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 6B86FBF2ABA; Tue, 13 Jun 2017 12:07:20 +0000 (UTC) (envelope-from mmel@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 45F6679350; Tue, 13 Jun 2017 12:07:20 +0000 (UTC) (envelope-from mmel@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id v5DC7JLC065382; Tue, 13 Jun 2017 12:07:19 GMT (envelope-from mmel@FreeBSD.org) Received: (from mmel@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id v5DC7Ih7065377; Tue, 13 Jun 2017 12:07:18 GMT (envelope-from mmel@FreeBSD.org) Message-Id: <201706131207.v5DC7Ih7065377@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: mmel set sender to mmel@FreeBSD.org using -f From: Michal Meloun Date: Tue, 13 Jun 2017 12:07:18 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r319896 - in head/sys/arm: arm include X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 13 Jun 2017 12:07:20 -0000 Author: mmel Date: Tue Jun 13 12:07:18 2017 New Revision: 319896 URL: https://svnweb.freebsd.org/changeset/base/319896 Log: Implement tunable CPU quirks. These quirks are intended for optimizing CPU performance, not for applying errata workarounds. Nobody can expect that CPU with unfixed errata is stable enough to execute the kernel until quirks are applied. MFC after: 3 weeks Modified: head/sys/arm/arm/cpuinfo.c head/sys/arm/arm/mp_machdep.c head/sys/arm/arm/pmap-v6.c head/sys/arm/include/cpuinfo.h head/sys/arm/include/pmap-v6.h Modified: head/sys/arm/arm/cpuinfo.c ============================================================================== --- head/sys/arm/arm/cpuinfo.c Tue Jun 13 10:52:31 2017 (r319895) +++ head/sys/arm/arm/cpuinfo.c Tue Jun 13 12:07:18 2017 (r319896) @@ -30,10 +30,15 @@ __FBSDID("$FreeBSD$"); #include #include +#include #include #include +#if __ARM_ARCH >= 6 +void reinit_mmu(uint32_t ttb, uint32_t aux_clr, uint32_t aux_set); +#endif + struct cpuinfo cpuinfo = { /* Use safe defaults for start */ @@ -43,6 +48,30 @@ struct cpuinfo cpuinfo = .icache_line_mask = 31, }; +static SYSCTL_NODE(_hw, OID_AUTO, cpu, CTLFLAG_RD, 0, + "CPU"); +static SYSCTL_NODE(_hw_cpu, OID_AUTO, quirks, CTLFLAG_RD, 0, + "CPU quirks"); + +/* + * Tunable CPU quirks. + * Be careful, ACTRL cannot be changed if CPU is started in secure + * mode(world) and write to ACTRL can cause exception! + * These quirks are intended for optimizing CPU performance, not for + * applying errata workarounds. Nobody can expect that CPU with unfixed + * errata is stable enough to execute the kernel until quirks are applied. + */ +static uint32_t cpu_quirks_actlr_mask; +SYSCTL_INT(_hw_cpu_quirks, OID_AUTO, actlr_mask, + CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &cpu_quirks_actlr_mask, 0, + "Bits to be masked in ACTLR"); + +static uint32_t cpu_quirks_actlr_set; +SYSCTL_INT(_hw_cpu_quirks, OID_AUTO, actlr_set, + CTLFLAG_RDTUN | CTLFLAG_NOFETCH, &cpu_quirks_actlr_set, 0, + "Bits to be set in ACTLR"); + + /* Read and parse CPU id scheme */ void cpuinfo_init(void) @@ -155,15 +184,17 @@ cpuinfo_init(void) #endif } +#if __ARM_ARCH >= 6 /* * Get bits that must be set or cleared in ACLR register. * Note: Bits in ACLR register are IMPLEMENTATION DEFINED. * Its expected that SCU is in operational state before this * function is called. */ -void +static void cpuinfo_get_actlr_modifier(uint32_t *actlr_mask, uint32_t *actlr_set) { + *actlr_mask = 0; *actlr_set = 0; @@ -238,3 +269,18 @@ cpuinfo_get_actlr_modifier(uint32_t *actlr_mask, uint3 return; } } + +/* Reinitialize MMU to final kernel mapping and apply all CPU quirks. */ +void +cpuinfo_reinit_mmu(uint32_t ttb) +{ + uint32_t actlr_mask; + uint32_t actlr_set; + + cpuinfo_get_actlr_modifier(&actlr_mask, &actlr_set); + actlr_mask |= cpu_quirks_actlr_mask; + actlr_set |= cpu_quirks_actlr_set; + reinit_mmu(ttb, actlr_mask, actlr_set); +} + +#endif /* __ARM_ARCH >= 6 */ Modified: head/sys/arm/arm/mp_machdep.c ============================================================================== --- head/sys/arm/arm/mp_machdep.c Tue Jun 13 10:52:31 2017 (r319895) +++ head/sys/arm/arm/mp_machdep.c Tue Jun 13 12:07:18 2017 (r319896) @@ -154,11 +154,9 @@ init_secondary(int cpu) #ifndef INTRNG int start = 0, end = 0; #endif - uint32_t actlr_mask, actlr_set; pmap_set_tex(); - cpuinfo_get_actlr_modifier(&actlr_mask, &actlr_set); - reinit_mmu(pmap_kern_ttb, actlr_mask, actlr_set); + cpuinfo_reinit_mmu(pmap_kern_ttb); cpu_setup(); /* Provide stack pointers for other processor modes. */ Modified: head/sys/arm/arm/pmap-v6.c ============================================================================== --- head/sys/arm/arm/pmap-v6.c Tue Jun 13 10:52:31 2017 (r319895) +++ head/sys/arm/arm/pmap-v6.c Tue Jun 13 12:07:18 2017 (r319896) @@ -763,7 +763,7 @@ pmap_bootstrap_prepare(vm_paddr_t last) pt1_entry_t *pte1p; pt2_entry_t *pte2p; u_int i; - uint32_t actlr_mask, actlr_set, l1_attr; + uint32_t l1_attr; /* * Now, we are going to make real kernel mapping. Note that we are @@ -880,8 +880,7 @@ pmap_bootstrap_prepare(vm_paddr_t last) /* Finally, switch from 'boot_pt1' to 'kern_pt1'. */ pmap_kern_ttb = base_pt1 | ttb_flags; - cpuinfo_get_actlr_modifier(&actlr_mask, &actlr_set); - reinit_mmu(pmap_kern_ttb, actlr_mask, actlr_set); + cpuinfo_reinit_mmu(pmap_kern_ttb); /* * Initialize the first available KVA. As kernel image is mapped by * sections, we are leaving some gap behind. Modified: head/sys/arm/include/cpuinfo.h ============================================================================== --- head/sys/arm/include/cpuinfo.h Tue Jun 13 10:52:31 2017 (r319895) +++ head/sys/arm/include/cpuinfo.h Tue Jun 13 12:07:18 2017 (r319896) @@ -124,5 +124,7 @@ struct cpuinfo { extern struct cpuinfo cpuinfo; void cpuinfo_init(void); -void cpuinfo_get_actlr_modifier(uint32_t *actlr_mask, uint32_t *actlr_set); +#if __ARM_ARCH >= 6 +void cpuinfo_reinit_mmu(uint32_t ttb); +#endif #endif /* _MACHINE_CPUINFO_H_ */ Modified: head/sys/arm/include/pmap-v6.h ============================================================================== --- head/sys/arm/include/pmap-v6.h Tue Jun 13 10:52:31 2017 (r319895) +++ head/sys/arm/include/pmap-v6.h Tue Jun 13 12:07:18 2017 (r319896) @@ -176,7 +176,6 @@ vm_paddr_t pmap_dump_kextract(vm_offset_t, pt2_entry_t int pmap_fault(pmap_t, vm_offset_t, uint32_t, int, bool); void pmap_set_tex(void); -void reinit_mmu(ttb_entry_t ttb, u_int aux_clr, u_int aux_set); /* * Pre-bootstrap epoch functions set.