From owner-svn-src-head@FreeBSD.ORG Tue Feb 14 20:34:25 2012 Return-Path: Delivered-To: svn-src-head@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 8AF9F106566C; Tue, 14 Feb 2012 20:34:25 +0000 (UTC) (envelope-from rwatson@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id 79E668FC1C; Tue, 14 Feb 2012 20:34:25 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.4/8.14.4) with ESMTP id q1EKYPxj017228; Tue, 14 Feb 2012 20:34:25 GMT (envelope-from rwatson@svn.freebsd.org) Received: (from rwatson@localhost) by svn.freebsd.org (8.14.4/8.14.4/Submit) id q1EKYPxd017226; Tue, 14 Feb 2012 20:34:25 GMT (envelope-from rwatson@svn.freebsd.org) Message-Id: <201202142034.q1EKYPxd017226@svn.freebsd.org> From: Robert Watson Date: Tue, 14 Feb 2012 20:34:25 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r231712 - head/sys/mips/mips X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 14 Feb 2012 20:34:25 -0000 Author: rwatson Date: Tue Feb 14 20:34:25 2012 New Revision: 231712 URL: http://svn.freebsd.org/changeset/base/231712 Log: When initialising the CP0 status register during boot on 64-bit MIPS, set all three of the kernel, supervisor, and user-mode 64-bit mode flags. While FreeBSD does not currently use the supervisor ring (and hence this is effectively a NOP on most systems), doing this avoids triggering an exception on 64-bit MIPS CPUs that don't support 32-bit compatibility mode, and therefore don't allow clearing the SX bit. Reviewed by: gonzo MFC after: 3 days Sponsored by: DARPA, SRI International Modified: head/sys/mips/mips/locore.S Modified: head/sys/mips/mips/locore.S ============================================================================== --- head/sys/mips/mips/locore.S Tue Feb 14 20:12:16 2012 (r231711) +++ head/sys/mips/mips/locore.S Tue Feb 14 20:34:25 2012 (r231712) @@ -118,7 +118,7 @@ VECTOR(_locore, unknown) */ li t1, MIPS_SR_COP_1_BIT #ifdef __mips_n64 - or t1, MIPS_SR_KX | MIPS_SR_UX + or t1, MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX #endif #endif /*