Skip site navigation (1)Skip section navigation (2)
Date:      Tue, 14 Feb 2012 20:34:25 +0000 (UTC)
From:      Robert Watson <rwatson@FreeBSD.org>
To:        src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org
Subject:   svn commit: r231712 - head/sys/mips/mips
Message-ID:  <201202142034.q1EKYPxd017226@svn.freebsd.org>

next in thread | raw e-mail | index | archive | help
Author: rwatson
Date: Tue Feb 14 20:34:25 2012
New Revision: 231712
URL: http://svn.freebsd.org/changeset/base/231712

Log:
  When initialising the CP0 status register during boot on 64-bit MIPS,
  set all three of the kernel, supervisor, and user-mode 64-bit mode
  flags.  While FreeBSD does not currently use the supervisor ring (and
  hence this is effectively a NOP on most systems), doing this avoids
  triggering an exception on 64-bit MIPS CPUs that don't support 32-bit
  compatibility mode, and therefore don't allow clearing the SX bit.
  
  Reviewed by:	gonzo
  MFC after:	3 days
  Sponsored by:	DARPA, SRI International

Modified:
  head/sys/mips/mips/locore.S

Modified: head/sys/mips/mips/locore.S
==============================================================================
--- head/sys/mips/mips/locore.S	Tue Feb 14 20:12:16 2012	(r231711)
+++ head/sys/mips/mips/locore.S	Tue Feb 14 20:34:25 2012	(r231712)
@@ -118,7 +118,7 @@ VECTOR(_locore, unknown)
 	 */
 	li	t1, MIPS_SR_COP_1_BIT
 #ifdef __mips_n64
-	or	t1, MIPS_SR_KX | MIPS_SR_UX
+	or	t1, MIPS_SR_KX | MIPS_SR_SX | MIPS_SR_UX
 #endif
 #endif
 	/*



Want to link to this message? Use this URL: <https://mail-archive.FreeBSD.org/cgi/mid.cgi?201202142034.q1EKYPxd017226>