From owner-freebsd-current@FreeBSD.ORG Thu Dec 8 14:57:04 2005 Return-Path: X-Original-To: freebsd-current@freebsd.org Delivered-To: freebsd-current@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id A88D316A420 for ; Thu, 8 Dec 2005 14:57:04 +0000 (GMT) (envelope-from jhb@freebsd.org) Received: from speedfactory.net (mail6.speedfactory.net [66.23.216.219]) by mx1.FreeBSD.org (Postfix) with ESMTP id 6EAC343D72 for ; Thu, 8 Dec 2005 14:56:51 +0000 (GMT) (envelope-from jhb@freebsd.org) Received: from server.baldwin.cx (unverified [66.23.211.162]) by speedfactory.net (SurgeMail 3.5b3) with ESMTP id 3386557 for multiple; Thu, 08 Dec 2005 09:58:52 -0500 Received: from zion.baldwin.cx (zion.baldwin.cx [192.168.0.7]) (authenticated bits=0) by server.baldwin.cx (8.13.1/8.13.1) with ESMTP id jB8EugVx071318; Thu, 8 Dec 2005 09:56:43 -0500 (EST) (envelope-from jhb@freebsd.org) From: John Baldwin To: "Darren Pilgrim" Date: Thu, 8 Dec 2005 09:37:21 -0500 User-Agent: KMail/1.8.3 References: <001801c5fb83$987529f0$642a15ac@smiley> In-Reply-To: <001801c5fb83$987529f0$642a15ac@smiley> MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Message-Id: <200512080937.22418.jhb@freebsd.org> X-Spam-Status: No, score=-2.8 required=4.2 tests=ALL_TRUSTED autolearn=failed version=3.0.2 X-Spam-Checker-Version: SpamAssassin 3.0.2 (2004-11-16) on server.baldwin.cx X-Server: High Performance Mail Server - http://surgemail.com r=1653887525 Cc: freebsd-current@freebsd.org Subject: Re: can someone explain...[ PCI interrupts] X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Dec 2005 14:57:04 -0000 On Wednesday 07 December 2005 06:11 pm, Darren Pilgrim wrote: > From: John Baldwin > > > No, PCI interrupts are level triggered. Individual APIC pins > > can be programmed to be edge-triggered, sure. However, then > > interrupts stop working if 2 devices are sharing a line and > > one interrupts after the other has already interrupted and > > after the second device's ISR has already run. In this case, > > the ithread will finish and go back to sleep waiting for an > > interrupt. However, since the ISR for the second device > > wasn't run after that device asserted its interrupt pin, the > > second device will keep the pin pulled low forever, so there > > will never be a hi -> low transition that the APIC pin would > > post an interrupt for and that intpin and all attached > > devices are effectively dead. > > What if the APIC was programmed to be edge-triggered just before the > ithread runs and programmed back to level-trigger when the ithread > completes? I'd rather work on my other solution which might be about 5 lines of code=20 rather than screw around with the APICs when that might have other side=20 effects. =2D-=20 John Baldwin =A0<>< =A0http://www.FreeBSD.org/~jhb/ "Power Users Use the Power to Serve" =A0=3D =A0http://www.FreeBSD.org