Date: Wed, 29 Oct 1997 20:12:30 +0000 (GMT) From: Terry Lambert <tlambert@primenet.com> To: karpen@ocean.campus.luth.se (Mikael Karpberg) Cc: dg@root.com, hackers@FreeBSD.ORG Subject: Re: Parity Ram Message-ID: <199710292012.NAA18109@usr07.primenet.com> In-Reply-To: <199710290229.DAA07708@ocean.campus.luth.se> from "Mikael Karpberg" at Oct 29, 97 03:29:12 am
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> > In order to update the memory, the ECC must be recalculated over the > > entire 64bit quadword. This escentially means that you have to read the > > memory first, apply the changes/calculate the new ECC and then write it > > back. Obviously,this makes memory writes quite a bit slower. > > Hmm... It's still not quite clear to me. That is, does this slow my > computer down, in case I use ECC? > > It seems to me all this could be done on the DIMM/SIMM, or something, > possibly clocked at multiple of the bus clockspeed, and therefor > not effect the rate at which memory could be read/written over the bus > by the CPU. I'd personally think using a static column dram would do the trick... Also, there's no real reson the write can't return and leave the cell calculating the ECC on it's on. It would make rereferencing the area take a wait, possibly, if the rereference was immediate. Terry Lambert terry@lambert.org --- Any opinions in this posting are my own and not those of my present or previous employers.
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