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From: Adrian Chadd <adrian@FreeBSD.org>
Date: Sun, 26 Aug 2012 04:39:20 +0000 (UTC)
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Subject: svn commit: r239706 - head/sys/mips/atheros
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Author: adrian
Date: Sun Aug 26 04:39:20 2012
New Revision: 239706
URL: http://svn.freebsd.org/changeset/base/239706

Log:
  Ensure that BAR(0) is set for the PCI slot before the ath(4) PCI registers
  are written out.
  
  This allows EEPROM-less NICs on the AR7241 PCIe bus to be correctly
  initialised.
  
  Tested:
  
  * AP91 (AR7240+AR9285) - the existing board support didn't break;
  * AP99 (AR7241+AR9287) - this fixed the configuration of the AR9287 PCI.

Modified:
  head/sys/mips/atheros/ar724x_pci.c

Modified: head/sys/mips/atheros/ar724x_pci.c
==============================================================================
--- head/sys/mips/atheros/ar724x_pci.c	Sun Aug 26 04:36:59 2012	(r239705)
+++ head/sys/mips/atheros/ar724x_pci.c	Sun Aug 26 04:39:20 2012	(r239706)
@@ -270,6 +270,10 @@ ar724x_pci_fixup(device_t dev, long flas
 	/* Save bar(0) address - just to flush bar(0) (SoC WAR) ? */
 	bar0 = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_BAR(0), 4);
 
+	/* Write temporary BAR0 to map the NIC into a fixed location */
+	ar724x_pci_write_config(dev, 0, 0, 0, PCIR_BAR(0),
+	    AR71XX_PCI_MEM_BASE, 4);
+
 	val = ar724x_pci_read_config(dev, 0, 0, 0, PCIR_COMMAND, 2);
 	val |= (PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN);
 	ar724x_pci_write_config(dev, 0, 0, 0, PCIR_COMMAND, val, 2);