From owner-freebsd-hardware  Wed Feb 12 00:15:13 1997
Return-Path: <owner-hardware>
Received: (from root@localhost)
          by freefall.freebsd.org (8.8.5/8.8.5) id AAA15032
          for hardware-outgoing; Wed, 12 Feb 1997 00:15:13 -0800 (PST)
Received: from bunyip.cc.uq.oz.au (daemon@bunyip.cc.uq.oz.au [130.102.2.1])
          by freefall.freebsd.org (8.8.5/8.8.5) with ESMTP id AAA15027
          for <freebsd-hardware@freebsd.org>; Wed, 12 Feb 1997 00:15:08 -0800 (PST)
Received: (from daemon@localhost)
	by bunyip.cc.uq.oz.au (8.8.5/8.8.5) id SAA04861
	for freebsd-hardware@freebsd.org; Wed, 12 Feb 1997 18:14:59 +1000
Received: by ogre.devetir.qld.gov.au (8.7.5/DEVETIR-E0.3a)
	id SAA25550; Wed, 12 Feb 1997 18:16:45 +1000 (EST)
Date: Wed, 12 Feb 1997 18:16:45 +1000 (EST)
From: Stephen McKay <syssgm@devetir.qld.gov.au>
Message-Id: <199702120816.SAA25550@ogre.devetir.qld.gov.au>
To: freebsd-hardware@freebsd.org
cc: Stephen McKay <syssgm@devetir.qld.gov.au>
Subject: Re: 64 MB ECC or 128 MB non ECC ?
X-Newsreader: NN version 6.5.0 #1 (NOV)
Sender: owner-hardware@freebsd.org
X-Loop: FreeBSD.org
Precedence: bulk

I wrote:

>The variation in individual runs was about 1% and I'm still a little
>concerned that maybe the ECC BIOS setting isn't doing anything at all.
>Cynical old me.  So, my next set of tests will be with L1 and L2 cache
>disabled to highlight the speed difference.  Much of this difference will
>be mopped up by the write merge buffers on the TXC, but it should still
>be bigger than 1%.

Well, I'm glad I've got some cache to enable since without cache the kernel
compile takes 15 times as long.  Yes, my ECC, nocache test took 97 minutes!
Yikes!  The final result is that ECC is 12% slower than PARITY with no cache.
(user+sys time only).  This is in agreement with those people who predicted
10-15% main memory slow down, but, as noted above, reduces to 1% with both
caches enabled.  1% is no pain at all.

>Final proof that the ECC setting does anything other than slow my machine
>down will have to wait until I work out how to reprogram the TXC to suddenly
>switch from PARITY to ECC.  This should immediately cause an ECC failure.

I've got the tech doc from Intel now, so I'll be able to try this soon.

Later,

Stephen.