Date: Sun, 20 Jan 2002 19:08:08 -0500 (EST) From: Garrett Wollman <wollman@khavrinen.lcs.mit.edu> To: louie@TransSys.COM Cc: arch@freebsd.org Subject: Re: 64 bit counters again Message-ID: <200201210008.g0L088333530@khavrinen.lcs.mit.edu> In-Reply-To: <mit.lcs.mail.freebsd-arch/200201202224.g0KMO8E56230@whizzo.transsys.com> References: <mit.lcs.mail.freebsd-arch/3C48A0E7.F97BC01@mindspring.com> <mit.lcs.mail.freebsd-arch/200201190350.g0J3oNN08944@khavrinen.lcs.mit.edu> <mit.lcs.mail.freebsd-arch/3C48FCEF.9190CA08@mindspring.com> <mit.lcs.mail.freebsd-arch/20020121082826.Z72285@gsmx07.alcatel.com.au>
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In article <mit.lcs.mail.freebsd-arch/200201202224.g0KMO8E56230@whizzo.transsys.com> you write: >On an SMP system, some sort of locking is required to reliably >update a 32 bit or 64 bit counter. [...] > - This can be a low-level architectural feature, such as the IA32 >LOCK prefix on an instruction to convert it into an atomic R-M-W >operation. Technically, atomic RMW is not considered locking. (Hence, the class of algorithms known as ``lock-free synchronization algorithms''.) -GAWollman -- Garrett A. Wollman | O Siem / We are all family / O Siem / We're all the same wollman@lcs.mit.edu | O Siem / The fires of freedom Opinions not those of| Dance in the burning flame MIT, LCS, CRS, or NSA| - Susan Aglukark and Chad Irschick To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-arch" in the body of the message
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