From owner-freebsd-current@FreeBSD.ORG Tue Feb 26 11:51:23 2008 Return-Path: Delivered-To: current@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id E90E2106585E; Tue, 26 Feb 2008 11:51:22 +0000 (UTC) (envelope-from ssouhlal@FreeBSD.org) Received: from elvis.mu.org (elvis.mu.org [192.203.228.196]) by mx1.freebsd.org (Postfix) with ESMTP id CC11C13E695; Tue, 26 Feb 2008 09:47:32 +0000 (UTC) (envelope-from ssouhlal@FreeBSD.org) Received: from [192.168.0.100] (c-76-21-32-5.hsd1.ca.comcast.net [76.21.32.5]) by elvis.mu.org (Postfix) with ESMTP id 8DE9E1A3C1A; Tue, 26 Feb 2008 01:47:32 -0800 (PST) In-Reply-To: <20080225215035.Q920@desktop> References: <20080225161855.M920@desktop> <47C37CAC.90806@freebsd.org> <20080225195402.M920@desktop> <47C3B943.8020407@freebsd.org> <20080225215035.Q920@desktop> Mime-Version: 1.0 (Apple Message framework v752.3) Content-Type: text/plain; charset=US-ASCII; delsp=yes; format=flowed Message-Id: Content-Transfer-Encoding: 7bit From: Suleiman Souhlal Date: Tue, 26 Feb 2008 01:47:21 -0800 To: Jeff Roberson X-Mailer: Apple Mail (2.752.3) Cc: David Xu , current@freebsd.org Subject: Re: Topology aware scheduling algorithm. X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Feb 2008 11:51:24 -0000 On Feb 25, 2008, at 11:51 PM, Jeff Roberson wrote: > > On Tue, 26 Feb 2008, David Xu wrote: > >> Jeff Roberson wrote: >> >>> I think our identcpu.c already detects this information. That's >>> what I'm using. Although I assume that all cpus are identical >>> and fall back on a flat topology if this isn't the case. I'd >>> like to start including more cache information though. >>> Jeff >> >> The patch does not assume all cpus are identical, in theory, one >> can have a machine with one cpu is 4-core and another is 2-core cpu. >> only one place needs to be fixed in the patch,the global variable >> cpu_feature, which is easy to fix for the patch. > > cpuid_count(4, cache_level, regs); > if ((regs[0] & 0x1f) == 0) > break; > threads_per_cache = ((regs[0] & 0x3ffc000) >> 14) + 1; > > Does this work on all intel/amd cpus? That won't work on AMD, as they don't support cpuid 4, as far as I know. -- Suleiman