From owner-freebsd-stable@FreeBSD.ORG Fri Jan 14 16:27:08 2005 Return-Path: Delivered-To: freebsd-stable@freebsd.org Received: from mx1.FreeBSD.org (mx1.freebsd.org [216.136.204.125]) by hub.freebsd.org (Postfix) with ESMTP id E5BAB16A4CE for ; Fri, 14 Jan 2005 16:27:08 +0000 (GMT) Received: from mail-in-03.arcor-online.net (mail-in-03.arcor-online.net [151.189.21.43]) by mx1.FreeBSD.org (Postfix) with ESMTP id 6E4DC43D48 for ; Fri, 14 Jan 2005 16:27:05 +0000 (GMT) (envelope-from mailnull@mips.inka.de) Received: from kemoauc.mips.inka.de (dsl-082-082-076-194.arcor-ip.net [82.82.76.194]) by mail-in-03.arcor-online.net (Postfix) with ESMTP id 8DB6D14FB50 for ; Fri, 14 Jan 2005 17:27:03 +0100 (CET) Received: from kemoauc.mips.inka.de (localhost [127.0.0.1]) by kemoauc.mips.inka.de (8.13.1/8.12.10) with ESMTP id j0EGR1fr019336 for ; Fri, 14 Jan 2005 17:27:01 +0100 (CET) (envelope-from mailnull@kemoauc.mips.inka.de) Received: (from mailnull@localhost) by kemoauc.mips.inka.de (8.13.1/8.13.1/Submit) id j0EGR1Tv019330 for freebsd-stable@freebsd.org; Fri, 14 Jan 2005 17:27:01 +0100 (CET) (envelope-from mailnull) From: naddy@mips.inka.de (Christian Weisgerber) Date: Fri, 14 Jan 2005 16:27:00 +0000 (UTC) Message-ID: Originator: naddy@mips.inka.de (Christian Weisgerber) To: freebsd-stable@freebsd.org Subject: 4.11: sysctl hw.instruction_sse? X-BeenThere: freebsd-stable@freebsd.org X-Mailman-Version: 2.1.1 Precedence: list List-Id: Production branch of FreeBSD source code List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 14 Jan 2005 16:27:09 -0000 I'm currently dealing with a report of ports/devel/flac dying in its optimized SSE code on a 4.11/i386 system. What's the status of SSE kernel support in 4.x? freefall and the user's machine report hw.instruction_sse=0, although they run on CPUs that do support SSE. Does RELENG_4 generally not provide SSE support? However, the SSE-related code in the repository (sys/i386/i386/{initcpu,machdep}.c) looks like that in RELENG_5. flac brings its own optimizations for MMX, SSE, etc, checks the CPU at runtime and uses the best code path. If we don't provide the kernel support for SSE on CPUs that have these instructions, then that's obviously a problem. freefall, 4.11-RC2: CPU: Intel Pentium III (801.82-MHz 686-class CPU) Origin = "GenuineIntel" Id = 0x686 Stepping = 6 Features=0x383f9ff hw.instruction_sse: 0 ref5jp, 5.2-CURRENT: CPU: Pentium III/Pentium III Xeon/Celeron (498.49-MHz 686-class CPU) Origin = "GenuineIntel" Id = 0x673 Stepping = 3 Features=0x383f9ff hw.instruction_sse: 1 What's going on here? -- Christian "naddy" Weisgerber naddy@mips.inka.de