From owner-svn-src-head@freebsd.org Mon Nov 30 17:09:27 2015 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 01B02A3C972; Mon, 30 Nov 2015 17:09:27 +0000 (UTC) (envelope-from mmel@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id D085A1AE5; Mon, 30 Nov 2015 17:09:26 +0000 (UTC) (envelope-from mmel@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id tAUH9PWH089515; Mon, 30 Nov 2015 17:09:25 GMT (envelope-from mmel@FreeBSD.org) Received: (from mmel@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id tAUH9P9E089512; Mon, 30 Nov 2015 17:09:25 GMT (envelope-from mmel@FreeBSD.org) Message-Id: <201511301709.tAUH9P9E089512@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: mmel set sender to mmel@FreeBSD.org using -f From: Michal Meloun Date: Mon, 30 Nov 2015 17:09:25 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r291492 - in head/sys/arm: arm include X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.20 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 Nov 2015 17:09:27 -0000 Author: mmel Date: Mon Nov 30 17:09:25 2015 New Revision: 291492 URL: https://svnweb.freebsd.org/changeset/base/291492 Log: ARM: create new memory attribute for writethrough cacheable memory. - add new TEX class for WT cacheable memory - export new TEX class to kernel as VM_MEMATTR_WT attribute - add new aliases VM_MEMATTR_WRITE_COMBINING and VM_MEMATTR_WRITE_BACK, it's used in DRM code Note: Only Cortex A8 supports WT caching in HW. On rest of Cortex CPUs, WT requests is treated as uncacheable. Approved by: kib (mentor) Modified: head/sys/arm/arm/pmap-v6-new.c head/sys/arm/include/pte-v6.h head/sys/arm/include/vm.h Modified: head/sys/arm/arm/pmap-v6-new.c ============================================================================== --- head/sys/arm/arm/pmap-v6-new.c Mon Nov 30 16:34:13 2015 (r291491) +++ head/sys/arm/arm/pmap-v6-new.c Mon Nov 30 17:09:25 2015 (r291492) @@ -388,14 +388,14 @@ pmap_debug(int level) static uint32_t tex_class[8] = { /* type inner cache outer cache */ - TEX(PRRR_MEM, NMRR_WB_WA, NMRR_WB_WA, 0), /* 0 - ATTR_WB_WA */ - TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 1 - ATTR_NOCACHE */ - TEX(PRRR_DEV, NMRR_NC, NMRR_NC, 0), /* 2 - ATTR_DEVICE */ - TEX(PRRR_SO, NMRR_NC, NMRR_NC, 0), /* 3 - ATTR_SO */ - TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 4 - NOT USED YET */ - TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 5 - NOT USED YET */ - TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 6 - NOT USED YET */ - TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 7 - NOT USED YET */ + TEX(PRRR_MEM, NMRR_WB_WA, NMRR_WB_WA, 0), /* 0 - ATTR_WB_WA */ + TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 1 - ATTR_NOCACHE */ + TEX(PRRR_DEV, NMRR_NC, NMRR_NC, 0), /* 2 - ATTR_DEVICE */ + TEX(PRRR_SO, NMRR_NC, NMRR_NC, 0), /* 3 - ATTR_SO */ + TEX(PRRR_MEM, NMRR_WT, NMRR_WT, 0), /* 4 - ATTR_WT */ + TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 5 - NOT USED YET */ + TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 6 - NOT USED YET */ + TEX(PRRR_MEM, NMRR_NC, NMRR_NC, 0), /* 7 - NOT USED YET */ }; #undef TEX Modified: head/sys/arm/include/pte-v6.h ============================================================================== --- head/sys/arm/include/pte-v6.h Mon Nov 30 16:34:13 2015 (r291491) +++ head/sys/arm/include/pte-v6.h Mon Nov 30 17:09:25 2015 (r291492) @@ -196,6 +196,7 @@ #define PTE2_ATTR_NOCACHE TEX2_CLASS_1 #define PTE2_ATTR_DEVICE TEX2_CLASS_2 #define PTE2_ATTR_SO TEX2_CLASS_3 +#define PTE2_ATTR_WT TEX2_CLASS_4 /* * Software defined bits for L1 descriptors * - L1_AP0 is used as page accessed bit Modified: head/sys/arm/include/vm.h ============================================================================== --- head/sys/arm/include/vm.h Mon Nov 30 16:34:13 2015 (r291491) +++ head/sys/arm/include/vm.h Mon Nov 30 17:09:25 2015 (r291492) @@ -32,14 +32,16 @@ #ifdef ARM_NEW_PMAP #include -#define VM_MEMATTR_WB_WA ((vm_memattr_t)PTE2_ATTR_WB_WA) -#define VM_MEMATTR_NOCACHE ((vm_memattr_t)PTE2_ATTR_NOCACHE) -#define VM_MEMATTR_DEVICE ((vm_memattr_t)PTE2_ATTR_DEVICE) -#define VM_MEMATTR_SO ((vm_memattr_t)PTE2_ATTR_SO) - -#define VM_MEMATTR_DEFAULT VM_MEMATTR_WB_WA -#define VM_MEMATTR_UNCACHEABLE VM_MEMATTR_SO /*name is misused by DMA */ +#define VM_MEMATTR_WB_WA ((vm_memattr_t)PTE2_ATTR_WB_WA) +#define VM_MEMATTR_NOCACHE ((vm_memattr_t)PTE2_ATTR_NOCACHE) +#define VM_MEMATTR_DEVICE ((vm_memattr_t)PTE2_ATTR_DEVICE) +#define VM_MEMATTR_SO ((vm_memattr_t)PTE2_ATTR_SO) +#define VM_MEMATTR_WT ((vm_memattr_t)PTE2_ATTR_WT) +#define VM_MEMATTR_DEFAULT VM_MEMATTR_WB_WA +#define VM_MEMATTR_UNCACHEABLE VM_MEMATTR_SO /* misused by DMA */ +#define VM_MEMATTR_WRITE_COMBINING VM_MEMATTR_WT /* for DRM */ +#define VM_MEMATTR_WRITE_BACK VM_MEMATTR_WB_WA /* for DRM */ #else /* Memory attribute configuration. */