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Date:      Sat, 31 Aug 2002 22:03:18 +1000 (EST)
From:      Bruce Evans <bde@zeta.org.au>
To:        Poul-Henning Kamp <phk@critter.freebsd.dk>
Cc:        hardware@FreeBSD.ORG
Subject:   Re: PCI latency timer vs interrupt latency and ISA bus latency 
Message-ID:  <20020831215409.C5111-100000@gamplex.bde.org>
In-Reply-To: <39131.1030787173@critter.freebsd.dk>

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On Sat, 31 Aug 2002, Poul-Henning Kamp wrote:

> In message <20020831160511.O3960-100000@gamplex.bde.org>, Bruce Evans writes:
>
> >Debugging of interrupt latency caused by critical_enter() showed that
> >DELAY(2) sometimes delayed for 170 or more usec for an Athlon1600 CPU
>
> DELAY(2) should not use i8254 when better alternatives exist.  We may
> not want to deal with the TSC calibration issue, but both the ACPI timer
> and the APIC timer in the CPU would be good candidates.

This is not the point here.  DELAY() is just the messenger.  What is
important is that bus accesses may be slowed down by a factor of 60 or
more for at least 3 accesses in succession, and that a using a simple
spinlock to provide exclusive access to the device and semi-exclusive
access to the CPU works surprisingly badly -- it prevents the CPU from
doing anything useful for 60 times longer than expected.

Bruce


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