From owner-freebsd-usb@FreeBSD.ORG Tue Dec 18 19:22:03 2012 Return-Path: Delivered-To: freebsd-usb@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [69.147.83.52]) by hub.freebsd.org (Postfix) with ESMTP id 3FB16B28; Tue, 18 Dec 2012 19:22:03 +0000 (UTC) (envelope-from andrew@fubar.geek.nz) Received: from smtp3.clear.net.nz (smtp3.clear.net.nz [203.97.33.64]) by mx1.freebsd.org (Postfix) with ESMTP id D72998FC8B; Tue, 18 Dec 2012 19:12:45 +0000 (UTC) Received: from mxin1-orange.clear.net.nz (lb2-srcnat.clear.net.nz [203.97.32.237]) by smtp3.clear.net.nz (CLEAR Net Mail) with ESMTP id <0MF800I1FQP2IM00@smtp3.clear.net.nz>; Wed, 19 Dec 2012 08:12:44 +1300 (NZDT) Received: from 202-0-48-19.paradise.net.nz (HELO localhost) ([202.0.48.19]) by smtpin1.paradise.net.nz with ESMTP; Wed, 19 Dec 2012 08:12:43 +1300 Date: Wed, 19 Dec 2012 08:12:29 +1300 From: Andrew Turner Subject: Re: EHCI on armv6 with Write-Back caches In-reply-to: <201212181306.44926.hselasky@c2i.net> To: Hans Petter Selasky Message-id: <20121219081229.383d9f41@fubar.geek.nz> MIME-version: 1.0 X-Mailer: Claws Mail 3.8.0 (GTK+ 2.24.6; i386-portbld-freebsd8.1) Content-type: text/plain; charset=US-ASCII Content-transfer-encoding: 7bit X-Pirate: Arrrr References: <20121218204931.5322922d@fubar.geek.nz> <201212180922.22217.hselasky@c2i.net> <20121219000213.269b1371@fubar.geek.nz> <201212181306.44926.hselasky@c2i.net> Cc: Oleksandr Tymoshenko , freebsd-usb@freebsd.org X-BeenThere: freebsd-usb@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: FreeBSD support for USB List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 18 Dec 2012 19:22:03 -0000 On Tue, 18 Dec 2012 13:06:44 +0100 Hans Petter Selasky wrote: > Hi Andrew, > > > The BUS_DMA_COHERENT flag does nothing on armv6 as we need the cache > > enabled for atomic operations to work correctly and we would have to > > disable the cache on the entire page. This is acceptable behaviour > > from the description of the flag in the busdma man page. > > Yes, but when I allocate memory from the USB stack, then I want that > memory to not be cached. It is simply not that useful to have that > memory cached. I didn't check the latest state of busdma, but if I'm > not mistaken, if the BUS_DMA_COHERENT flag is set on the DMA tag, the > flush/invalidate will simply return and do nothing. Maybe that is the > problem ... The exact meaning of BUS_DMA_COHERENT depends on the architecture. The code is still required to call bus_dmamap_sync with a coherent map but when the flag is implemented the cost of the operation will be reduced. It doesn't guarantee the memory is uncached, it may be implemented that way but the USB code can't rely on it. Andrew