From owner-freebsd-current@FreeBSD.ORG Tue Feb 26 11:52:12 2008 Return-Path: Delivered-To: current@hub.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 14F251065BD3 for ; Tue, 26 Feb 2008 11:52:11 +0000 (UTC) (envelope-from davidxu@FreeBSD.org) Received: from freefall.freebsd.org (freefall.freebsd.org [IPv6:2001:4f8:fff6::28]) by mx1.freebsd.org (Postfix) with ESMTP id 6AE5B13D893; Tue, 26 Feb 2008 09:00:00 +0000 (UTC) (envelope-from davidxu@FreeBSD.org) Received: from apple.my.domain (root@localhost [127.0.0.1]) by freefall.freebsd.org (8.14.2/8.14.2) with ESMTP id m1Q8xvWU072896; Tue, 26 Feb 2008 08:59:59 GMT (envelope-from davidxu@freebsd.org) Message-ID: <47C3D55A.10905@freebsd.org> Date: Tue, 26 Feb 2008 17:01:14 +0800 From: David Xu User-Agent: Thunderbird 2.0.0.9 (X11/20071211) MIME-Version: 1.0 To: Jeff Roberson References: <20080225161855.M920@desktop> <47C37CAC.90806@freebsd.org> <20080225195402.M920@desktop> <47C3B943.8020407@freebsd.org> <20080225215035.Q920@desktop> In-Reply-To: <20080225215035.Q920@desktop> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Cc: current@FreeBSD.org Subject: Re: Topology aware scheduling algorithm. X-BeenThere: freebsd-current@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Discussions about the use of FreeBSD-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 26 Feb 2008 11:52:13 -0000 Jeff Roberson wrote: > > On Tue, 26 Feb 2008, David Xu wrote: > >> Jeff Roberson wrote: >> >>> I think our identcpu.c already detects this information. That's what >>> I'm using. Although I assume that all cpus are identical and fall >>> back on a flat topology if this isn't the case. I'd like to start >>> including more cache information though. >>> >>> Jeff >> >> The patch does not assume all cpus are identical, in theory, one can >> have a machine with one cpu is 4-core and another is 2-core cpu. >> only one place needs to be fixed in the patch,the global variable >> cpu_feature, which is easy to fix for the patch. > > cpuid_count(4, cache_level, regs); > if ((regs[0] & 0x1f) == 0) > break; > threads_per_cache = ((regs[0] & 0x3ffc000) >> 14) + 1; > > Does this work on all intel/amd cpus? > I can not find similar functions in amd's document. http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/25481.pdf however they seems to have updated the document for their new cpu which sharing L3. The extended function 0x80000006 now reports L3 information in register %edx. They have never shared L2, so you can assume when the %edx is nonzero, it is now a cache-shared cpu, otherwise cpus on same package just use crossbar to communicate with each other, it is still better than old front-bus, scheduler may think about this performance improvement. > Thanks, > Jeff