From owner-freebsd-stable@FreeBSD.ORG Wed Aug 25 16:03:54 2010 Return-Path: Delivered-To: freebsd-stable@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 80EA51065698; Wed, 25 Aug 2010 16:03:54 +0000 (UTC) (envelope-from avg@icyb.net.ua) Received: from citadel.icyb.net.ua (citadel.icyb.net.ua [212.40.38.140]) by mx1.freebsd.org (Postfix) with ESMTP id 9177C8FC14; Wed, 25 Aug 2010 16:03:53 +0000 (UTC) Received: from odyssey.starpoint.kiev.ua (alpha-e.starpoint.kiev.ua [212.40.38.101]) by citadel.icyb.net.ua (8.8.8p3/ICyb-2.3exp) with ESMTP id TAA06538; Wed, 25 Aug 2010 19:03:51 +0300 (EEST) (envelope-from avg@icyb.net.ua) Message-ID: <4C753EE7.3010805@icyb.net.ua> Date: Wed, 25 Aug 2010 19:03:51 +0300 From: Andriy Gapon User-Agent: Mozilla/5.0 (X11; U; FreeBSD amd64; en-US; rv:1.9.2.8) Gecko/20100823 Lightning/1.0b2 Thunderbird/3.1.2 MIME-Version: 1.0 To: John Baldwin References: <4C71CC62.6060803@langille.org> <4C745213.3050004@langille.org> <201008250823.11954.jhb@freebsd.org> <4C75308F.3080504@icyb.net.ua> In-Reply-To: <4C75308F.3080504@icyb.net.ua> X-Enigmail-Version: 1.1.2 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Cc: freebsd-stable@freebsd.org Subject: Re: kernel MCA messages X-BeenThere: freebsd-stable@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Production branch of FreeBSD source code List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 25 Aug 2010 16:03:54 -0000 on 25/08/2010 18:02 Andriy Gapon said the following: > on 25/08/2010 15:23 John Baldwin said the following: >> That is because machine checks for corrected errors have to be polled and the >> kernel polls once an hour. On newer Intel CPUs (such as Nehalem) there is a >> separate interrupt (CMCI) that can fire for corrected errors. > > I think that on AMD it's possible to configure an interrupt for Bank 4 events as > well (perhaps other banks too), but I need to refresh my memory of BKDG. Yeah, for Bank 4 only, configurable via MSR0000_0413 and MSRC000_04[0A:08] Machine Check Misc 4 (Thresholding) Registers. Also, see section 2.12.1.6 Error Thresholding in Fam10h BKDG. -- Andriy Gapon