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Date:      Tue, 14 May 1996 09:41:04 -0700 (PDT)
From:      "Rodney W. Grimes" <rgrimes@GndRsh.aac.dev.com>
To:        mmead@Glock.COM (matthew c. mead)
Cc:        joerg_wunsch@uriah.heep.sax.de, blh@nol.net, jgreco@brasil.moneng.mei.com, hackers@freebsd.org, hardware@freebsd.org
Subject:   Re: Triton chipset with 256k cache caches 32M only?
Message-ID:  <199605141641.JAA04309@GndRsh.aac.dev.com>
In-Reply-To: <199605141313.JAA07905@Glock.COM> from "matthew c. mead" at "May 14, 96 09:13:28 am"

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> J Wunsch writes:
> 
> > As Brett L. Hawn wrote:
> 
> > >  I would highly suggest getting some of the new
> > > ASUS (just my particular favorite) tr-2 chipset motherboards, these solve
> > > the caching problem along with many of the other inherent bugs of tr-1
> > > chipsets.
> 
> > They even can do ECC now if you're using parity SIMMs!
> 
> > (About to get my new board into service by tomorrow or thursday. :)
> 
> 	I'd really like to do ECC, I just don't have the money for it right
> now.  So does this ECC work the same as the ECC on DEC Alphas?  On the Alphas,
> you put in 5M for every 4M of addressable ram.  Is there a fifth simm slot on
> these motherboards where a non ECC capable motherboard would have 4?

No, this does not work the way you describe the Alpha working.

You simply use 72 pin x 36 bit simms in pairs.  64 bits of data requires
8 bits to do ECC _OR_ byte parity.  There is a setting in the BIOS that
allows you to choose either ECC mode or Parity mode.  Choosing ECC gives
you the warm fuzzies, but it costs you 10 to 15% in memory bandwidth.



-- 
Rod Grimes                                      rgrimes@gndrsh.aac.dev.com
Accurate Automation Company                 Reliable computers for FreeBSD



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