From owner-svn-src-head@freebsd.org Tue Nov 15 07:08:34 2016 Return-Path: Delivered-To: svn-src-head@mailman.ysv.freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:1900:2254:206a::19:1]) by mailman.ysv.freebsd.org (Postfix) with ESMTP id 85F25C42523; Tue, 15 Nov 2016 07:08:34 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from repo.freebsd.org (repo.freebsd.org [IPv6:2610:1c1:1:6068::e6a:0]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by mx1.freebsd.org (Postfix) with ESMTPS id 5DA7F1E8; Tue, 15 Nov 2016 07:08:34 +0000 (UTC) (envelope-from manu@FreeBSD.org) Received: from repo.freebsd.org ([127.0.1.37]) by repo.freebsd.org (8.15.2/8.15.2) with ESMTP id uAF78Xdp022179; Tue, 15 Nov 2016 07:08:33 GMT (envelope-from manu@FreeBSD.org) Received: (from manu@localhost) by repo.freebsd.org (8.15.2/8.15.2/Submit) id uAF78XBN022176; Tue, 15 Nov 2016 07:08:33 GMT (envelope-from manu@FreeBSD.org) Message-Id: <201611150708.uAF78XBN022176@repo.freebsd.org> X-Authentication-Warning: repo.freebsd.org: manu set sender to manu@FreeBSD.org using -f From: Emmanuel Vadot Date: Tue, 15 Nov 2016 07:08:33 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org Subject: svn commit: r308672 - in head/sys: arm/allwinner arm/allwinner/clk boot/fdt/dts/arm X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-BeenThere: svn-src-head@freebsd.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: SVN commit messages for the src tree for head/-current List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 15 Nov 2016 07:08:34 -0000 Author: manu Date: Tue Nov 15 07:08:33 2016 New Revision: 308672 URL: https://svnweb.freebsd.org/changeset/base/308672 Log: Upstream DTS provides PLL3 and PLL7 nodes (and their x2 form), so remove them from our DTS and adapt the code to handle them correctly. This fix HDMI video on A20. Modified: head/sys/arm/allwinner/a10_hdmi.c head/sys/arm/allwinner/clk/aw_pll.c head/sys/boot/fdt/dts/arm/sun7i-a20-hdmi.dtsi Modified: head/sys/arm/allwinner/a10_hdmi.c ============================================================================== --- head/sys/arm/allwinner/a10_hdmi.c Tue Nov 15 06:37:44 2016 (r308671) +++ head/sys/arm/allwinner/a10_hdmi.c Tue Nov 15 07:08:33 2016 (r308672) @@ -581,7 +581,7 @@ a10hdmi_get_tcon_config(struct a10hdmi_s /* Detect LCD CH1 special clock using a 1X or 2X source */ /* XXX */ pname = clk_get_name(clk_lcd_parent); - if (strcmp(pname, "pll3-1x") == 0 || strcmp(pname, "pll7-1x") == 0) + if (strcmp(pname, "pll3") == 0 || strcmp(pname, "pll7") == 0) *dbl = 0; else *dbl = 1; Modified: head/sys/arm/allwinner/clk/aw_pll.c ============================================================================== --- head/sys/arm/allwinner/clk/aw_pll.c Tue Nov 15 06:37:44 2016 (r308671) +++ head/sys/arm/allwinner/clk/aw_pll.c Tue Nov 15 07:08:33 2016 (r308672) @@ -180,9 +180,6 @@ __FBSDID("$FreeBSD$"); #define H3_PLL2_PRE_DIV (0x1f << 0) #define H3_PLL2_PRE_DIV_SHIFT 0 -#define CLKID_A10_PLL3_1X 0 -#define CLKID_A10_PLL3_2X 1 - #define CLKID_A10_PLL5_DDR 0 #define CLKID_A10_PLL5_OTHER 1 @@ -476,9 +473,6 @@ a10_pll3_recalc(struct aw_pll_sc *sc, ui *freq = 297000000; } - if (sc->id == CLKID_A10_PLL3_2X) - *freq *= 2; - return (0); } @@ -489,14 +483,10 @@ a10_pll3_set_freq(struct aw_pll_sc *sc, uint32_t val, m, mode, func; m = *fout / A10_PLL3_REF_FREQ; - if (sc->id == CLKID_A10_PLL3_2X) - m /= 2; mode = A10_PLL3_MODE_SEL_INT; func = 0; *fout = m * A10_PLL3_REF_FREQ; - if (sc->id == CLKID_A10_PLL3_2X) - *fout *= 2; DEVICE_LOCK(sc); PLL_READ(sc, &val); Modified: head/sys/boot/fdt/dts/arm/sun7i-a20-hdmi.dtsi ============================================================================== --- head/sys/boot/fdt/dts/arm/sun7i-a20-hdmi.dtsi Tue Nov 15 06:37:44 2016 (r308671) +++ head/sys/boot/fdt/dts/arm/sun7i-a20-hdmi.dtsi Tue Nov 15 07:08:33 2016 (r308672) @@ -28,25 +28,11 @@ / { clocks { - pll3: clk@01c20010 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20010 0x4>; - clock-output-names = "pll3-1x", "pll3-2x"; - }; - - pll7: clk@01c20030 { - #clock-cells = <1>; - compatible = "allwinner,sun4i-a10-pll3-clk"; - reg = <0x01c20030 0x4>; - clock-output-names = "pll7-1x", "pll7-2x"; - }; - hdmi_clk: clk@01c20150 { #clock-cells = <0>; compatible = "allwinner,sun4i-a10-hdmi-clk"; reg = <0x01c20150 0x4>; - clocks = <&pll3 0>, <&pll7 0>, <&pll3 1>, <&pll7 1>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; clock-output-names = "hdmi"; }; @@ -55,7 +41,7 @@ #reset-cells = <0>; compatible = "allwinner,sun4i-a10-lcd-ch0-clk"; reg = <0x01c20118 0x4>; - clocks = <&pll3 0>, <&pll7 0>, <&pll3 1>, <&pll6 2>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll6 2>; clock-output-names = "lcd0_ch0"; }; @@ -63,7 +49,7 @@ #clock-cells = <1>; compatible = "allwinner,sun4i-a10-lcd-ch1-clk"; reg = <0x01c2012c 0x4>; - clocks = <&pll3 0>, <&pll7 0>, <&pll3 1>, <&pll7 1>; + clocks = <&pll3>, <&pll7>, <&pll3x2>, <&pll7x2>; clock-output-names = "lcd0_ch1_sclk1", "lcd0_ch1_sclk2"; }; @@ -73,7 +59,7 @@ #reset-cells = <0>; compatible = "allwinner,sun4i-a10-de-be-clk"; reg = <0x01c20104 0x4>; - clocks = <&pll3 0>, <&pll7 0>, <&pll5 1>; + clocks = <&pll3>, <&pll7>, <&pll5 1>; clock-output-names = "de_be0"; }; };