From owner-freebsd-arm@FreeBSD.ORG Thu Oct 8 16:13:57 2009 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 118921065670 for ; Thu, 8 Oct 2009 16:13:57 +0000 (UTC) (envelope-from tinguely@casselton.net) Received: from casselton.net (casselton.net [63.165.140.2]) by mx1.freebsd.org (Postfix) with ESMTP id BCB998FC08 for ; Thu, 8 Oct 2009 16:13:56 +0000 (UTC) Received: from casselton.net (localhost [127.0.0.1]) by casselton.net (8.14.3/8.14.3) with ESMTP id n98GDtAM053540; Thu, 8 Oct 2009 11:13:55 -0500 (CDT) (envelope-from tinguely@casselton.net) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=casselton.net; s=ccnMail; t=1255018435; bh=NpxRtCj9M0cYJlfTZ6bCBaAiErIuHcVdbIIS5jH6jjc=; h=Date:From:Message-Id:To:Subject:In-Reply-To; b=HkNaxfqtXpm/ePfxOvcyZ54LmLwcq2NX8BXLvNqOsMXFZkUjt5E5sY3GfSKucCqZ9 1tORCiQ0X5oDxcnvkmhCKxorwkE/MCcccPw5BZUCVohuUIIg+x2NNPL1M5t15WgfNx 2x/BiznLEWhW66oekSTNXDjWjRfTVYT54oSoCSBc= Received: (from tinguely@localhost) by casselton.net (8.14.3/8.14.2/Submit) id n98GDt7r053539; Thu, 8 Oct 2009 11:13:55 -0500 (CDT) (envelope-from tinguely) Date: Thu, 8 Oct 2009 11:13:55 -0500 (CDT) From: Mark Tinguely Message-Id: <200910081613.n98GDt7r053539@casselton.net> To: freebsd-arm@freebsd.org, gballet@gmail.com In-Reply-To: X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.3.2 (casselton.net [127.0.0.1]); Thu, 08 Oct 2009 11:13:55 -0500 (CDT) Cc: Subject: Re: Adding members to struct cpu_functions X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 08 Oct 2009 16:13:57 -0000 > I am continuing my effort to port FreeBSD to the BeagleBoard. I > reached the point where the system prompts for the root filesystem. I > am therefore cleaning up my code and will then post it to this list > for comments. I still have a few hacky fixups to remove before it > becomes readable :) Congratulations. > I know that Mark Tinguely, whose help has been precious in this > endeavor, has some patches ready for ARMv6 cache management, so I did > not focus on this. It is all untested. I am wondering to myself with small number of TBL on the OMAP, should we use the new ASID process identifier and not flush the TBLs or just flush them on context switch. > At the moment, I am using backward-compatibility for the TLB format. I > want to start using the ARMv6 TLB format. My current problem is that > most of the arch-dependent code uses macros that are defined to match > the pre-ARMv6 TLB format. There are several ways of fixing this, > including defining these macros depending on some symbol such as > _ARM_ARCH_* or CPU_ARM*. I am however no friend of heavy preprocessor > flagging. What if instead, cpu_functions was extended to include > fields like the prototype for TLB entries of each size? For example, > take this patch to the following excerpt from pmap_map_chunk in > sys/arm/arm/pmap.c: [deleted example] > Now, assuming people agree with this change, that would only be a > first step because all values for cpufuncs are defined in the same > file (cpufunc.c), which is guarded with as many CPU_ARMx defines as > there are cpu flavors. Is there a specific reason for all these > structures to be defined in a same file, instead of defining it in a > platform- or cpu-specific file and using the files.* to select the > appropriate cpufunc flavor in the build system? I have been pondering the current L1/L2 (in this context we mean Page Directory entries and Page Table entries, not cache levels) values for cache, protection, the C/B/TEX (and now the global, secure, and no execute) and masks for a while. Some of these values are variables and some are defines. It can be confusing to track down a value for a ARCH/board. ARM kernels are very specific for processor and board. IMO, we should be moving some of these settings into a processor [and board] directories/files and make them more consistant. I am not saying anything bad about NetBSD that originate these files nor the additions that have been made since, what I am saying is it would be nice to have a big reorganization; that takes time and therefore money. -- on a tangent about the future -- Since the ARMv7 is coming to FreeBSD, there are other ARMv4/5 vrs ARMv6/7 questions, the most important is should we break the new ARM chips with their physical tagged caches to another subbranch or define it into the existing code? One example of the existing pmap code that does not mesh well with ARMv6/7 is the exisiting flush of the level 2 cache because the old archs have VIVT level 2 caches). ARMv6/7 level 2 caches are PIPT, and would not be flushed until DMA time. A simple solution would be if an arch needs to flush the level 2 cache when it flushes the level 1 cache, then it should do so in the level 1 cache flushing routine. --Mark Tinguely.