From owner-p4-projects@FreeBSD.ORG Thu Oct 16 13:29:00 2008 Return-Path: Delivered-To: p4-projects@freebsd.org Received: by hub.freebsd.org (Postfix, from userid 32767) id E940E106568C; Thu, 16 Oct 2008 13:28:59 +0000 (UTC) Delivered-To: perforce@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id AB60C1065687 for ; Thu, 16 Oct 2008 13:28:59 +0000 (UTC) (envelope-from zec@tel.fer.hr) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 981A18FC08 for ; Thu, 16 Oct 2008 13:28:59 +0000 (UTC) (envelope-from zec@tel.fer.hr) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.3/8.14.3) with ESMTP id m9GDSxhT040417 for ; Thu, 16 Oct 2008 13:28:59 GMT (envelope-from zec@tel.fer.hr) Received: (from perforce@localhost) by repoman.freebsd.org (8.14.3/8.14.3/Submit) id m9GDSw9r040415 for perforce@freebsd.org; Thu, 16 Oct 2008 13:28:58 GMT (envelope-from zec@tel.fer.hr) Date: Thu, 16 Oct 2008 13:28:58 GMT Message-Id: <200810161328.m9GDSw9r040415@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: perforce set sender to zec@tel.fer.hr using -f From: Marko Zec To: Perforce Change Reviews Cc: Subject: PERFORCE change 151453 for review X-BeenThere: p4-projects@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: p4 projects tree changes List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 16 Oct 2008 13:29:00 -0000 http://perforce.freebsd.org/chv.cgi?CH=151453 Change 151453 by zec@zec_tpx32 on 2008/10/16 13:28:21 IFC @ 151449 Affected files ... .. //depot/projects/vimage-commit2/src/sys/amd64/amd64/vm_machdep.c#3 integrate .. //depot/projects/vimage-commit2/src/sys/amd64/conf/GENERIC#7 integrate .. //depot/projects/vimage-commit2/src/sys/amd64/linux32/linux.h#2 integrate .. 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//depot/projects/vimage-commit2/src/sys/sys/pmc.h#3 integrate .. //depot/projects/vimage-commit2/src/sys/sys/proc.h#6 integrate .. //depot/projects/vimage-commit2/src/sys/sys/tty.h#5 integrate .. //depot/projects/vimage-commit2/src/sys/sys/un.h#2 integrate .. //depot/projects/vimage-commit2/src/sys/sys/vnode.h#5 integrate .. //depot/projects/vimage-commit2/src/sys/ufs/ffs/ffs_inode.c#3 integrate .. //depot/projects/vimage-commit2/src/sys/ufs/ffs/ffs_snapshot.c#4 integrate .. //depot/projects/vimage-commit2/src/sys/ufs/ffs/ffs_vfsops.c#7 integrate .. //depot/projects/vimage-commit2/src/sys/vm/vm_object.c#4 integrate Differences ... ==== //depot/projects/vimage-commit2/src/sys/amd64/amd64/vm_machdep.c#3 (text+ko) ==== @@ -41,7 +41,7 @@ */ #include -__FBSDID("$FreeBSD: src/sys/amd64/amd64/vm_machdep.c,v 1.258 2008/09/11 18:33:57 jhb Exp $"); +__FBSDID("$FreeBSD: src/sys/amd64/amd64/vm_machdep.c,v 1.259 2008/10/05 02:03:54 davidxu Exp $"); #include "opt_isa.h" #include "opt_cpu.h" @@ -280,6 +280,14 @@ */ bcopy(td0->td_frame, td->td_frame, sizeof(struct trapframe)); + /* If the current thread has the trap bit set (i.e. a debugger had + * single stepped the process to the system call), we need to clear + * the trap flag from the new frame. Otherwise, the new thread will + * receive a (likely unexpected) SIGTRAP when it executes the first + * instruction after returning to userland. + */ + td->td_frame->tf_rflags &= ~PSL_T; + /* * Set registers for trampoline to user mode. Leave space for the * return address on stack. These are the kernel mode register values. ==== //depot/projects/vimage-commit2/src/sys/amd64/conf/GENERIC#7 (text+ko) ==== @@ -16,7 +16,7 @@ # If you are in doubt as to the purpose or necessity of a line, check first # in NOTES. # -# $FreeBSD: src/sys/amd64/conf/GENERIC,v 1.507 2008/08/20 08:31:58 ed Exp $ +# $FreeBSD: src/sys/amd64/conf/GENERIC,v 1.508 2008/10/03 10:31:31 stas Exp $ cpu HAMMER ident GENERIC @@ -200,6 +200,7 @@ # PCI Ethernet NICs that use the common MII bus controller code. # NOTE: Be sure to keep the 'device miibus' line in order to use these NICs! device miibus # MII bus support +device ae # Attansic/Atheros L2 FastEthernet device age # Attansic/Atheros L1 Gigabit Ethernet device bce # Broadcom BCM5706/BCM5708 Gigabit Ethernet device bfe # Broadcom BCM440x 10/100 Ethernet ==== //depot/projects/vimage-commit2/src/sys/amd64/linux32/linux.h#2 (text+ko) ==== @@ -27,7 +27,7 @@ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. * - * $FreeBSD: src/sys/amd64/linux32/linux.h,v 1.17 2008/04/08 09:45:47 kib Exp $ + * $FreeBSD: src/sys/amd64/linux32/linux.h,v 1.18 2008/10/14 07:59:23 kib Exp $ */ #ifndef _AMD64_LINUX_H_ @@ -880,4 +880,15 @@ (LINUX_CLONE_VM | LINUX_CLONE_FS | LINUX_CLONE_FILES | \ LINUX_CLONE_SIGHAND | LINUX_CLONE_THREAD) +/* robust futexes */ +struct linux_robust_list { + l_uintptr_t next; +}; + +struct linux_robust_list_head { + struct linux_robust_list list; + l_ulong futex_offset; + l_uintptr_t pending_list; +}; + #endif /* !_AMD64_LINUX_H_ */ ==== //depot/projects/vimage-commit2/src/sys/arm/arm/busdma_machdep.c#2 (text+ko) ==== @@ -29,7 +29,7 @@ */ #include -__FBSDID("$FreeBSD: src/sys/arm/arm/busdma_machdep.c,v 1.38 2008/03/12 15:31:37 raj Exp $"); +__FBSDID("$FreeBSD: src/sys/arm/arm/busdma_machdep.c,v 1.39 2008/10/13 18:59:59 raj Exp $"); /* * ARM bus dma support routines @@ -629,6 +629,8 @@ newmap->allocbuffer = tmpaddr; cpu_idcache_wbinv_range((vm_offset_t)*vaddr, dmat->maxsize); + cpu_l2cache_wbinv_range((vm_offset_t)*vaddr, + dmat->maxsize); *vaddr = tmpaddr; } else newmap->origbuffer = newmap->allocbuffer = NULL; ==== //depot/projects/vimage-commit2/src/sys/arm/arm/cpufunc.c#2 (text+ko) ==== @@ -45,7 +45,7 @@ * Created : 30/01/97 */ #include -__FBSDID("$FreeBSD: src/sys/arm/arm/cpufunc.c,v 1.22 2007/11/28 22:55:55 cognet Exp $"); +__FBSDID("$FreeBSD: src/sys/arm/arm/cpufunc.c,v 1.23 2008/10/13 18:16:54 raj Exp $"); #include #include @@ -357,6 +357,66 @@ arm10_setup /* cpu setup */ }; + +struct cpu_functions feroceon_cpufuncs = { + /* CPU functions */ + + cpufunc_id, /* id */ + cpufunc_nullop, /* cpwait */ + + /* MMU functions */ + + cpufunc_control, /* control */ + cpufunc_domains, /* Domain */ + feroceon_setttb, /* Setttb */ + cpufunc_faultstatus, /* Faultstatus */ + cpufunc_faultaddress, /* Faultaddress */ + + /* TLB functions */ + + armv4_tlb_flushID, /* tlb_flushID */ + arm10_tlb_flushID_SE, /* tlb_flushID_SE */ + armv4_tlb_flushI, /* tlb_flushI */ + arm10_tlb_flushI_SE, /* tlb_flushI_SE */ + armv4_tlb_flushD, /* tlb_flushD */ + armv4_tlb_flushD_SE, /* tlb_flushD_SE */ + + /* Cache operations */ + + armv5_ec_icache_sync_all, /* icache_sync_all */ + armv5_ec_icache_sync_range, /* icache_sync_range */ + + armv5_ec_dcache_wbinv_all, /* dcache_wbinv_all */ + feroceon_dcache_wbinv_range, /* dcache_wbinv_range */ + feroceon_dcache_inv_range, /* dcache_inv_range */ + feroceon_dcache_wb_range, /* dcache_wb_range */ + + armv5_ec_idcache_wbinv_all, /* idcache_wbinv_all */ + feroceon_idcache_wbinv_range, /* idcache_wbinv_all */ + + feroceon_l2cache_wbinv_all, /* l2cache_wbinv_all */ + feroceon_l2cache_wbinv_range, /* l2cache_wbinv_range */ + feroceon_l2cache_inv_range, /* l2cache_inv_range */ + feroceon_l2cache_wb_range, /* l2cache_wb_range */ + + /* Other functions */ + + cpufunc_nullop, /* flush_prefetchbuf */ + armv4_drain_writebuf, /* drain_writebuf */ + cpufunc_nullop, /* flush_brnchtgt_C */ + (void *)cpufunc_nullop, /* flush_brnchtgt_E */ + + (void *)cpufunc_nullop, /* sleep */ + + /* Soft functions */ + + cpufunc_null_fixup, /* dataabt_fixup */ + cpufunc_null_fixup, /* prefetchabt_fixup */ + + arm10_context_switch, /* context_switch */ + + arm10_setup /* cpu setup */ +}; #endif /* CPU_ARM9E || CPU_ARM10 */ #ifdef CPU_ARM10 @@ -933,9 +993,36 @@ } #endif /* CPU_ARM9 */ #if defined(CPU_ARM9E) || defined(CPU_ARM10) - if (cputype == CPU_ID_ARM926EJS || - cputype == CPU_ID_ARM1026EJS) { - cpufuncs = armv5_ec_cpufuncs; + if (cputype == CPU_ID_ARM926EJS || cputype == CPU_ID_ARM1026EJS || + cputype == CPU_ID_MV88FR131 || cputype == CPU_ID_MV88FR571_VD || + cputype == CPU_ID_MV88FR571_41) { + if (cputype == CPU_ID_MV88FR131 || + cputype == CPU_ID_MV88FR571_VD || + cputype == CPU_ID_MV88FR571_41) { + + cpufuncs = feroceon_cpufuncs; + /* + * Workaround for Marvell MV78100 CPU: Cache prefetch + * mechanism may affect the cache coherency validity, + * so it needs to be disabled. + * + * Refer to errata document MV-S501058-00C.pdf (p. 3.1 + * L2 Prefetching Mechanism) for details. + */ + if (cputype == CPU_ID_MV88FR571_VD || + cputype == CPU_ID_MV88FR571_41) { + feroceon_control_ext(0xffffffff, + FC_DCACHE_STREAM_EN | FC_WR_ALLOC_EN | + FC_BRANCH_TARG_BUF_DIS | FC_L2CACHE_EN | + FC_L2_PREF_DIS); + } else { + feroceon_control_ext(0xffffffff, + FC_DCACHE_STREAM_EN | FC_WR_ALLOC_EN | + FC_BRANCH_TARG_BUF_DIS | FC_L2CACHE_EN); + } + } else + cpufuncs = armv5_ec_cpufuncs; + cpu_reset_needs_v4_MMU_disable = 1; /* V4 or higher */ get_cachetype_cp15(); pmap_pte_init_generic(); ==== //depot/projects/vimage-commit2/src/sys/arm/arm/elf_machdep.c#3 (text+ko) ==== @@ -24,7 +24,7 @@ */ #include -__FBSDID("$FreeBSD: src/sys/arm/arm/elf_machdep.c,v 1.8 2008/09/24 10:14:37 kib Exp $"); +__FBSDID("$FreeBSD: src/sys/arm/arm/elf_machdep.c,v 1.9 2008/10/13 18:59:59 raj Exp $"); #include #include @@ -215,6 +215,7 @@ { cpu_idcache_wbinv_all(); + cpu_l2cache_wbinv_all(); cpu_tlb_flushID(); return (0); } ==== //depot/projects/vimage-commit2/src/sys/arm/arm/elf_trampoline.c#3 (text+ko) ==== @@ -23,7 +23,7 @@ */ #include -__FBSDID("$FreeBSD: src/sys/arm/arm/elf_trampoline.c,v 1.21 2008/08/04 14:37:32 cognet Exp $"); +__FBSDID("$FreeBSD: src/sys/arm/arm/elf_trampoline.c,v 1.22 2008/10/13 20:07:13 raj Exp $"); #include #include #include @@ -73,6 +73,8 @@ #endif #ifdef CPU_XSCALE_81342 #define cpu_l2cache_wbinv_all xscalec3_l2cache_purge +#elif defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY) +#define cpu_l2cache_wbinv_all feroceon_l2cache_wbinv_all #else #define cpu_l2cache_wbinv_all() #endif ==== //depot/projects/vimage-commit2/src/sys/arm/arm/genassym.c#4 (text+ko) ==== @@ -26,7 +26,7 @@ */ #include -__FBSDID("$FreeBSD: src/sys/arm/arm/genassym.c,v 1.11 2008/02/05 10:22:33 raj Exp $"); +__FBSDID("$FreeBSD: src/sys/arm/arm/genassym.c,v 1.12 2008/10/13 18:59:59 raj Exp $"); #include #include #include @@ -79,7 +79,9 @@ ASSYM(CF_CONTROL, offsetof(struct cpu_functions, cf_control)); ASSYM(CF_CONTEXT_SWITCH, offsetof(struct cpu_functions, cf_context_switch)); ASSYM(CF_DCACHE_WB_RANGE, offsetof(struct cpu_functions, cf_dcache_wb_range)); +ASSYM(CF_L2CACHE_WB_RANGE, offsetof(struct cpu_functions, cf_l2cache_wb_range)); ASSYM(CF_IDCACHE_WBINV_ALL, offsetof(struct cpu_functions, cf_idcache_wbinv_all)); +ASSYM(CF_L2CACHE_WBINV_ALL, offsetof(struct cpu_functions, cf_l2cache_wbinv_all)); ASSYM(CF_TLB_FLUSHID_SE, offsetof(struct cpu_functions, cf_tlb_flushID_SE)); ASSYM(CF_ICACHE_SYNC, offsetof(struct cpu_functions, cf_icache_sync_all)); ==== //depot/projects/vimage-commit2/src/sys/arm/arm/identcpu.c#2 (text+ko) ==== @@ -42,7 +42,7 @@ */ #include -__FBSDID("$FreeBSD: src/sys/arm/arm/identcpu.c,v 1.13 2008/05/23 04:03:53 alc Exp $"); +__FBSDID("$FreeBSD: src/sys/arm/arm/identcpu.c,v 1.14 2008/10/13 18:16:54 raj Exp $"); #include #include #include @@ -75,7 +75,8 @@ CPU_CLASS_ARM10EJ, CPU_CLASS_SA1, CPU_CLASS_XSCALE, - CPU_CLASS_ARM11J + CPU_CLASS_ARM11J, + CPU_CLASS_MARVELL }; static const char * const generic_steppings[16] = { @@ -304,6 +305,15 @@ { CPU_ID_ARM1136JSR1, CPU_CLASS_ARM11J, "ARM1136J-S R1", generic_steppings }, + { CPU_ID_MV88FR131, CPU_CLASS_MARVELL, "Feroceon 88FR131", + generic_steppings }, + + { CPU_ID_MV88FR571_VD, CPU_CLASS_MARVELL, "Feroceon 88FR571-VD", + generic_steppings }, + + { CPU_ID_MV88FR571_41, CPU_CLASS_MARVELL, "Early Feroceon 88FR571", + generic_steppings }, + { 0, CPU_CLASS_NONE, NULL, NULL } }; ==== //depot/projects/vimage-commit2/src/sys/arm/arm/locore.S#2 (text+ko) ==== @@ -37,7 +37,7 @@ #include #include #include -__FBSDID("$FreeBSD: src/sys/arm/arm/locore.S,v 1.19 2008/04/08 10:24:41 kevlo Exp $"); +__FBSDID("$FreeBSD: src/sys/arm/arm/locore.S,v 1.21 2008/10/14 10:11:14 raj Exp $"); /* What size should this really be ? It is only used by initarm() */ #define INIT_ARM_STACK_SIZE 2048 @@ -66,6 +66,13 @@ ENTRY_NP(btext) ASENTRY_NP(_start) + +/* + * Move metadata ptr to r12 (ip) + */ + + mov ip, r0 + #if defined (FLASHADDR) && defined(LOADERRAMADDR) /* Check if we're running from flash. */ ldr r7, =FLASHADDR @@ -170,6 +177,8 @@ ldr pc, .Lvirt_done virt_done: + mov r0, ip /* Load argument: metadata ptr */ + mov fp, #0 /* trace back starts here */ bl _C_LABEL(initarm) /* Off we go */ @@ -245,6 +254,8 @@ ldr r0, .Lcpufuncs mov lr, pc ldr pc, [r0, #CF_IDCACHE_WBINV_ALL] + mov lr, pc + ldr pc, [r0, #CF_L2CACHE_WBINV_ALL] /* * Load the cpu_reset_needs_v4_MMU_disable flag to determine if it's ==== //depot/projects/vimage-commit2/src/sys/arm/arm/pmap.c#3 (text+ko) ==== @@ -147,10 +147,11 @@ #include "opt_vm.h" #include -__FBSDID("$FreeBSD: src/sys/arm/arm/pmap.c,v 1.102 2008/09/28 05:36:25 imp Exp $"); +__FBSDID("$FreeBSD: src/sys/arm/arm/pmap.c,v 1.104 2008/10/13 18:59:59 raj Exp $"); #include #include #include +#include #include #include #include @@ -1196,27 +1197,104 @@ } static PMAP_INLINE void +pmap_l2cache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len) +{ + vm_size_t rest; + pd_entry_t *pde; + pt_entry_t *ptep; + + rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len); + + while (len > 0) { + CTR4(KTR_PMAP, "pmap_l2cache_wbinv_range: pmap %p is_kernel %d " + "va 0x%08x len 0x%x ", pm, pm == pmap_kernel(), va, rest); + if (pmap_get_pde_pte(pm, va, &pde, &ptep) && l2pte_valid(*ptep)) + cpu_l2cache_wb_range(va, rest); + + len -= rest; + va += rest; + + rest = MIN(PAGE_SIZE, len); + } +} + +static PMAP_INLINE void pmap_idcache_wbinv_range(pmap_t pm, vm_offset_t va, vm_size_t len) { - if (pmap_is_current(pm)) + if (pmap_is_current(pm)) { cpu_idcache_wbinv_range(va, len); + pmap_l2cache_wbinv_range(pm, va, len); + } } static PMAP_INLINE void -pmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, - boolean_t do_inv, boolean_t rd_only) +pmap_l2cache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len) +{ + vm_size_t rest; + pd_entry_t *pde; + pt_entry_t *ptep; + + rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len); + + while (len > 0) { + CTR4(KTR_PMAP, "pmap_l2cache_wb_range: pmap %p is_kernel %d " + "va 0x%08x len 0x%x ", pm, pm == pmap_kernel(), va, rest); + if (pmap_get_pde_pte(pm, va, &pde, &ptep) && l2pte_valid(*ptep)) + cpu_l2cache_wb_range(va, rest); + + len -= rest; + va += rest; + + rest = MIN(PAGE_SIZE, len); + } +} + +static PMAP_INLINE void +pmap_l2cache_inv_range(pmap_t pm, vm_offset_t va, vm_size_t len) { + vm_size_t rest; + pd_entry_t *pde; + pt_entry_t *ptep; + + rest = MIN(PAGE_SIZE - (va & PAGE_MASK), len); + + while (len > 0) { + CTR4(KTR_PMAP, "pmap_l2cache_wb_range: pmap %p is_kernel %d " + "va 0x%08x len 0x%x ", pm, pm == pmap_kernel(), va, rest); + if (pmap_get_pde_pte(pm, va, &pde, &ptep) && l2pte_valid(*ptep)) + cpu_l2cache_inv_range(va, rest); + + len -= rest; + va += rest; + rest = MIN(PAGE_SIZE, len); + } +} + +static PMAP_INLINE void +pmap_dcache_wb_range(pmap_t pm, vm_offset_t va, vm_size_t len, boolean_t do_inv, + boolean_t rd_only) +{ + CTR4(KTR_PMAP, "pmap_dcache_wb_range: pmap %p is_kernel %d va 0x%08x " + "len 0x%x ", pm, pm == pmap_kernel(), va, len); + CTR2(KTR_PMAP, " do_inv %d rd_only %d", do_inv, rd_only); + if (pmap_is_current(pm)) { if (do_inv) { - if (rd_only) + if (rd_only) { cpu_dcache_inv_range(va, len); - else + pmap_l2cache_inv_range(pm, va, len); + } + else { cpu_dcache_wbinv_range(va, len); + pmap_l2cache_wbinv_range(pm, va, len); + } } else - if (!rd_only) + if (!rd_only) { cpu_dcache_wb_range(va, len); + pmap_l2cache_wb_range(pm, va, len); + } } } @@ -1224,16 +1302,20 @@ pmap_idcache_wbinv_all(pmap_t pm) { - if (pmap_is_current(pm)) + if (pmap_is_current(pm)) { cpu_idcache_wbinv_all(); + cpu_l2cache_wbinv_all(); + } } static PMAP_INLINE void pmap_dcache_wbinv_all(pmap_t pm) { - if (pmap_is_current(pm)) + if (pmap_is_current(pm)) { cpu_dcache_wbinv_all(); + cpu_l2cache_wbinv_all(); + } } /* @@ -2169,6 +2251,8 @@ PTE_SYNC(pdep); cpu_dcache_wbinv_range((vm_offset_t)pdep, sizeof(*pdep)); + cpu_l2cache_wbinv_range((vm_offset_t)pdep, + sizeof(*pdep)); rv = 1; } } else { @@ -2185,6 +2269,8 @@ PTE_SYNC(ptep); cpu_dcache_wbinv_range((vm_offset_t)ptep, sizeof(*ptep)); + cpu_l2cache_wbinv_range((vm_offset_t)ptep, + sizeof(*ptep)); rv = 1; } } @@ -2337,6 +2423,7 @@ } cpu_dcache_wbinv_all(); + cpu_l2cache_wbinv_all(); cpu_tlb_flushID(); cpu_cpwait(); @@ -2373,6 +2460,7 @@ mtx_init(&l1_lru_lock, "l1 list lock", NULL, MTX_DEF); pmap_init_l1(l1, kernel_l1pt); cpu_dcache_wbinv_all(); + cpu_l2cache_wbinv_all(); virtual_avail = round_page(virtual_avail); virtual_end = lastaddr; @@ -2402,6 +2490,7 @@ struct pcb *pcb; pmap_idcache_wbinv_all(pmap); + cpu_l2cache_wbinv_all(); pmap_tlb_flushID(pmap); cpu_cpwait(); if (vector_page < KERNBASE) { @@ -2589,6 +2678,7 @@ * rarely */ cpu_dcache_wbinv_all(); + cpu_l2cache_wbinv_all(); cpu_tlb_flushD(); cpu_cpwait(); kernel_vm_end = pmap_curmaxkvaddr; @@ -2614,6 +2704,7 @@ vm_page_lock_queues(); PMAP_LOCK(pmap); cpu_idcache_wbinv_all(); + cpu_l2cache_wbinv_all(); for (pv = TAILQ_FIRST(&pmap->pm_pvlist); pv; pv = npv) { if (pv->pv_flags & PVF_WIRED) { /* The page is wired, cannot remove it now. */ @@ -2726,6 +2817,7 @@ (uint32_t) pte, opte, *pte)); if (l2pte_valid(opte)) { cpu_dcache_wbinv_range(va, PAGE_SIZE); + cpu_l2cache_wbinv_range(va, PAGE_SIZE); cpu_tlb_flushD_SE(va); cpu_cpwait(); } else { @@ -2784,6 +2876,7 @@ opte = *pte; if (l2pte_valid(opte)) { cpu_dcache_wbinv_range(va, PAGE_SIZE); + cpu_l2cache_wbinv_range(va, PAGE_SIZE); cpu_tlb_flushD_SE(va); cpu_cpwait(); *pte = 0; @@ -3052,6 +3145,9 @@ u_int flags; int flush; + CTR4(KTR_PMAP, "pmap_protect: pmap %p sva 0x%08x eva 0x%08x prot %x", + pm, sva, eva, prot); + if ((prot & VM_PROT_READ) == 0) { pmap_remove(pm, sva, eva); return; @@ -3286,9 +3382,11 @@ */ if (pmap_is_current(pmap) && (oflags & PVF_NC) == 0 && - (opte & L2_S_PROT_W) != 0 && - (prot & VM_PROT_WRITE) == 0) + (opte & L2_S_PROT_W) != 0 && + (prot & VM_PROT_WRITE) == 0) { cpu_dcache_wb_range(va, PAGE_SIZE); + pmap_l2cache_wb_range(pmap, va, PAGE_SIZE); + } } else { /* * New mapping, or changing the backing page @@ -3777,11 +3875,15 @@ total++; if (is_exec) { cpu_idcache_wbinv_range(sva, - PAGE_SIZE); + PAGE_SIZE); + cpu_l2cache_wbinv_range(sva, + PAGE_SIZE); cpu_tlb_flushID_SE(sva); } else if (is_refd) { cpu_dcache_wbinv_range(sva, - PAGE_SIZE); + PAGE_SIZE); + cpu_l2cache_wbinv_range(sva, + PAGE_SIZE); cpu_tlb_flushD_SE(sva); } } else if (total == PMAP_REMOVE_CLEAN_LIST_SIZE) { @@ -3789,6 +3891,7 @@ * for a current pmap */ cpu_idcache_wbinv_all(); + cpu_l2cache_wbinv_all(); flushall = 1; total++; } @@ -3842,29 +3945,29 @@ if (off || size != PAGE_SIZE) { bzero(dstpg + off, size); cpu_dcache_wbinv_range((vm_offset_t)(dstpg + off), size); + cpu_l2cache_wbinv_range((vm_offset_t)(dstpg + off), size); } else { bzero_page((vm_offset_t)dstpg); cpu_dcache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE); + cpu_l2cache_wbinv_range((vm_offset_t)dstpg, PAGE_SIZE); } #else >>> TRUNCATED FOR MAIL (1000 lines) <<<