From owner-freebsd-arm@FreeBSD.ORG Sun Sep 29 20:01:42 2013 Return-Path: Delivered-To: freebsd-arm@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [8.8.178.115]) (using TLSv1 with cipher ADH-AES256-SHA (256/256 bits)) (No client certificate requested) by hub.freebsd.org (Postfix) with ESMTP id 9758E89C; Sun, 29 Sep 2013 20:01:42 +0000 (UTC) (envelope-from jiashiun@gmail.com) Received: from mail-vb0-x22b.google.com (mail-vb0-x22b.google.com [IPv6:2607:f8b0:400c:c02::22b]) (using TLSv1 with cipher ECDHE-RSA-RC4-SHA (128/128 bits)) (No client certificate requested) by mx1.freebsd.org (Postfix) with ESMTPS id 475EC2672; Sun, 29 Sep 2013 20:01:42 +0000 (UTC) Received: by mail-vb0-f43.google.com with SMTP id h11so3149248vbh.2 for ; Sun, 29 Sep 2013 13:01:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=mime-version:in-reply-to:references:from:date:message-id:subject:to :cc:content-type; bh=GBleBB1rmIXc6SYcBokFgiDZ3BlYeTFFaHappeUEiwQ=; b=atTNsHV6CbjVBoUb8AJ1L4DrqQ619ckQT7pJtlqy0DlW4EMtdW76WqEjLl66hk2O1d 2+zbyKOivBVfIk3WktHGuTaTn9U9Ue7p1rtwoSAN1D3dVxg4ZMXf3agzCzC1dpEvpE8S KjxTj4MBuOEWVnpPZluM2TdsJtRE1KCYfG4IpTSrLKIWcBZkMs9ARYm6XN7ynDvgfaJ3 QHk91WxfNPeWTNWarbVUQgEuJ0cinfZopbaae3DZ5nlEwWw8JW/RDvaXqniqUuqPqZ03 teDUB5dSW+OEqbb3ed7jYxOOu7pD69abPPfvUw5SgrIc3yKYy0mdUJwxTXSxlfbni7zT ZGMw== X-Received: by 10.220.174.200 with SMTP id u8mr18529813vcz.6.1380484901240; Sun, 29 Sep 2013 13:01:41 -0700 (PDT) MIME-Version: 1.0 Received: by 10.58.225.34 with HTTP; Sun, 29 Sep 2013 13:01:11 -0700 (PDT) In-Reply-To: References: From: Jia-Shiun Li Date: Mon, 30 Sep 2013 04:01:11 +0800 Message-ID: Subject: Re: BBB CPU clock (was: Re: FreeBSD on Cubieboard 2, UDOO and Galaxy Note 10.1 (Exynos). To: ticso@cicely.de Content-Type: text/plain; charset=UTF-8 Cc: "freebsd-arm@freebsd.org" X-BeenThere: freebsd-arm@freebsd.org X-Mailman-Version: 2.1.14 Precedence: list List-Id: Porting FreeBSD to the StrongARM Processor List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sun, 29 Sep 2013 20:01:42 -0000 On Mon, Sep 30, 2013 at 12:41 AM, Jia-Shiun Li wrote: > But I manually modified registers using the sequence in mpu_pll_config() of > u-boot and got the MPU clocked at the value I gave. There seems to be some > unknown sequences in u-boot either skipping or overwriting MPU PLL settings. Never mind. Have to copy MLO in addition to u-boot.img as well. Looks like PLL init part is there. However, I cannot set MPU clock to 800 MHz and beyond. Now booting ok at 750MHz. Maybe a heat sink or active cooling is required. Will try when I get one. cpufreq for ARM boards may be possible provided frequency can be changed dynamically. But if the board cannot provide a way to determine stability reliability it may be impractical to make it automatic. Jia-Shiun.