From owner-svn-src-all@FreeBSD.ORG Mon Feb 8 20:12:01 2010 Return-Path: Delivered-To: svn-src-all@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id CBD8C106566B; Mon, 8 Feb 2010 20:12:01 +0000 (UTC) (envelope-from rpaulo@FreeBSD.org) Received: from svn.freebsd.org (svn.freebsd.org [IPv6:2001:4f8:fff6::2c]) by mx1.freebsd.org (Postfix) with ESMTP id BA4A78FC1B; Mon, 8 Feb 2010 20:12:01 +0000 (UTC) Received: from svn.freebsd.org (localhost [127.0.0.1]) by svn.freebsd.org (8.14.3/8.14.3) with ESMTP id o18KC1Yi045201; Mon, 8 Feb 2010 20:12:01 GMT (envelope-from rpaulo@svn.freebsd.org) Received: (from rpaulo@localhost) by svn.freebsd.org (8.14.3/8.14.3/Submit) id o18KC1cu045193; Mon, 8 Feb 2010 20:12:01 GMT (envelope-from rpaulo@svn.freebsd.org) Message-Id: <201002082012.o18KC1cu045193@svn.freebsd.org> From: Rui Paulo Date: Mon, 8 Feb 2010 20:12:01 +0000 (UTC) To: src-committers@freebsd.org, svn-src-all@freebsd.org, svn-src-head@freebsd.org X-SVN-Group: head MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Cc: Subject: svn commit: r203682 - in head/sys/dev/ath/ath_hal: . ar5416 X-BeenThere: svn-src-all@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: "SVN commit messages for the entire src tree \(except for " user" and " projects" \)" List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 08 Feb 2010 20:12:01 -0000 Author: rpaulo Date: Mon Feb 8 20:12:01 2010 New Revision: 203682 URL: http://svn.freebsd.org/changeset/base/203682 Log: Fix TX power problems with AR9285. Modified: head/sys/dev/ath/ath_hal/ah_eeprom_v14.h head/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c head/sys/dev/ath/ath_hal/ar5416/ar5416phy.h head/sys/dev/ath/ath_hal/ar5416/ar9280.c head/sys/dev/ath/ath_hal/ar5416/ar9280.h head/sys/dev/ath/ath_hal/ar5416/ar9280_attach.c Modified: head/sys/dev/ath/ath_hal/ah_eeprom_v14.h ============================================================================== --- head/sys/dev/ath/ath_hal/ah_eeprom_v14.h Mon Feb 8 20:04:16 2010 (r203681) +++ head/sys/dev/ath/ath_hal/ah_eeprom_v14.h Mon Feb 8 20:12:01 2010 (r203682) @@ -14,7 +14,7 @@ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. * - * $Id: ah_eeprom_v14.h,v 1.3 2008/11/10 04:08:00 sam Exp $ + * $FreeBSD$ */ #ifndef _AH_EEPROM_V14_H_ #define _AH_EEPROM_V14_H_ @@ -76,6 +76,7 @@ #define AR5416_EEPMISC_BIG_ENDIAN 0x01 #define FREQ2FBIN(x,y) ((y) ? ((x) - 2300) : (((x) - 4800) / 5)) #define AR5416_MAX_CHAINS 3 +#define AR5416_PWR_TABLE_OFFSET_DB -5 #define AR5416_ANT_16S 25 #define AR5416_NUM_ANT_CHAIN_FIELDS 7 Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c Mon Feb 8 20:04:16 2010 (r203681) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416_cal.c Mon Feb 8 20:12:01 2010 (r203682) @@ -172,12 +172,11 @@ ar5416InitCal(struct ath_hal *ah, const ichan = ath_hal_checkchannel(ah, chan); HALASSERT(ichan != AH_NULL); - if (AR_SREV_KITE_12_OR_LATER(ah)) { - /* Clear the carrier leak cal bit */ OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); - if (IEEE80211_IS_CHAN_HT20(chan)) { + OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, + AR_PHY_CL_CAL_ENABLE); OS_REG_SET_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_PARALLEL_CAL_ENABLE); OS_REG_SET_BIT(ah, AR_PHY_TURBO, AR_PHY_FC_DYN2040_EN); @@ -191,7 +190,7 @@ ar5416InitCal(struct ath_hal *ah, const if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { HALDEBUG(ah, HAL_DEBUG_ANY, - "%s: offset calibration failed to " + "%s: HT offset calibration failed to " "complete in 1ms; noisy environment?\n", __func__); return AH_FALSE; @@ -201,14 +200,10 @@ ar5416InitCal(struct ath_hal *ah, const AR_PHY_PARALLEL_CAL_ENABLE); } OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); - - /* Enable Rx Filter Cal */ OS_REG_CLR_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_FLTR_CAL); OS_REG_SET_BIT(ah, AR_PHY_TPCRG1, AR_PHY_TPCRG1_PD_CAL_ENABLE); - - /* kick off the cal */ OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); /* Poll for offset calibration complete */ @@ -219,8 +214,6 @@ ar5416InitCal(struct ath_hal *ah, const "noisy environment?\n", __func__); return AH_FALSE; } - /* Set the cl cal bit and rerun the cal a 2nd time */ - /* Enable Rx Filter Cal */ OS_REG_SET_BIT(ah, AR_PHY_ADC_CTL, AR_PHY_ADC_CTL_OFF_PWDADC); OS_REG_CLR_BIT(ah, AR_PHY_CL_CAL_CTL, AR_PHY_CL_CAL_ENABLE); OS_REG_CLR_BIT(ah, AR_PHY_AGC_CONTROL, @@ -258,9 +251,10 @@ ar5416InitCal(struct ath_hal *ah, const OS_REG_SET_BIT(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL); /* Poll for offset calibration complete */ - if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, AR_PHY_AGC_CONTROL_CAL, 0)) { + if (!ath_hal_wait(ah, AR_PHY_AGC_CONTROL, + AR_PHY_AGC_CONTROL_CAL, 0)) { HALDEBUG(ah, HAL_DEBUG_ANY, - "%s: offset calibration did not complete in 1ms; " + "%s: AGC offset calibration did not complete in 1ms; " "noisy environment?\n", __func__); return AH_FALSE; } Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Mon Feb 8 20:04:16 2010 (r203681) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416_reset.c Mon Feb 8 20:12:01 2010 (r203682) @@ -898,6 +898,8 @@ ar5416SetTransmitPower(struct ath_hal *a ratesArray[i] = (int16_t)(txPowerIndexOffset + ratesArray[i]); if (ratesArray[i] > AR5416_MAX_RATE_POWER) ratesArray[i] = AR5416_MAX_RATE_POWER; + if (AR_SREV_MERLIN_10_OR_LATER(ah)) + ratesArray[i] -= AR5416_PWR_TABLE_OFFSET_DB * 2; } #ifdef AH_EEPROM_DUMP @@ -1225,7 +1227,7 @@ ar5416SetBoardValues(struct ath_hal *ah, const struct ar5416eeprom_4k *eep4k; const MODAL_EEP_HEADER *pModal; const MODAL_EEP4K_HEADER *pModal4k; - int i, regChainOffset; + int i, regChainOffset = 0; uint8_t txRxAttenLocal; /* workaround for eeprom versions <= 14.2 */ HALASSERT(AH_PRIVATE(ah)->ah_eeversion >= AR_EEPROM_VER14_1); @@ -1253,9 +1255,9 @@ ar5416SetBoardValues(struct ath_hal *ah, (pModal) ? pModal->antCtrlCommon : pModal4k->antCtrlCommon); for (i = 0; i < AR5416_MAX_CHAINS; i++) { - if (AR_SREV_KITE(ah) && i >= 1) break; - if (AR_SREV_MERLIN(ah) && i >= 2) break; - if (AR_SREV_OWL_20_OR_LATER(ah) && +// if (AR_SREV_KITE(ah) && i >= 2) break; + if (AR_SREV_MERLIN(ah) && i >= 2) break; + if (AR_SREV_OWL_20_OR_LATER(ah) && (AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5) && i != 0) { /* Regs are swapped from chain 2 to 1 for 5416 2_0 with @@ -1289,15 +1291,23 @@ ar5416SetBoardValues(struct ath_hal *ah, } else txRxAtten = txRxAttenLocal; - OS_REG_WRITE(ah, AR_PHY_RXGAIN + regChainOffset, - (OS_REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & ~AR_PHY_RXGAIN_TXRX_ATTEN) | - SM(txRxAtten, AR_PHY_RXGAIN_TXRX_ATTEN)); - - OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset, - (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) | - SM((pModal) ? pModal->rxTxMarginCh[i]: - pModal4k->rxTxMarginCh[i], - AR_PHY_GAIN_2GHZ_RXTX_MARGIN)); + if (AR_SREV_MERLIN_10_OR_LATER(ah)) { + OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, + AR9280_PHY_RXGAIN_TXRX_ATTEN, txRxAtten); + OS_REG_RMW_FIELD(ah, AR_PHY_RXGAIN + regChainOffset, + AR9280_PHY_RXGAIN_TXRX_MARGIN, + (pModal) ? pModal->rxTxMarginCh[i] : pModal4k->rxTxMarginCh[i]); + } else { + OS_REG_WRITE(ah, AR_PHY_RXGAIN + regChainOffset, + (OS_REG_READ(ah, AR_PHY_RXGAIN + regChainOffset) & ~AR_PHY_RXGAIN_TXRX_ATTEN) | + SM(txRxAtten, AR_PHY_RXGAIN_TXRX_ATTEN)); + + OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + regChainOffset, + (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + regChainOffset) & ~AR_PHY_GAIN_2GHZ_RXTX_MARGIN) | + SM((pModal) ? pModal->rxTxMarginCh[i]: + pModal4k->rxTxMarginCh[i], + AR_PHY_GAIN_2GHZ_RXTX_MARGIN)); + } } } @@ -1360,6 +1370,20 @@ ar5416SetBoardValues(struct ath_hal *ah, OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) | SM(pModal->bswAtten[1], AR_PHY_GAIN_2GHZ_BSW_ATTEN)); } else { + if (AR_SREV_MERLIN_10_OR_LATER(ah)) { + OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, + AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN, + (pModal) ? pModal->bswMargin[i] : pModal4k->bswMargin[i]); + OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, + AR_PHY_GAIN_2GHZ_XATTEN1_DB, + (pModal) ? pModal->bswAtten[i] : pModal4k->bswAtten[i]); + OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, + AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN, + (pModal) ? pModal->xatten2Margin[i] : pModal4k->xatten2Margin[i]); + OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ + regChainOffset, + AR_PHY_GAIN_2GHZ_XATTEN2_DB, + (pModal) ? pModal->xatten2Db[i] : pModal4k->xatten2Db[i]); + } else { OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x1000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x1000) & ~AR_PHY_GAIN_2GHZ_BSW_MARGIN) | SM((pModal) ? pModal->bswMargin[1] : pModal4k->bswMargin[1], AR_PHY_GAIN_2GHZ_BSW_MARGIN)); @@ -1372,6 +1396,7 @@ ar5416SetBoardValues(struct ath_hal *ah, OS_REG_WRITE(ah, AR_PHY_GAIN_2GHZ + 0x2000, (OS_REG_READ(ah, AR_PHY_GAIN_2GHZ + 0x2000) & ~AR_PHY_GAIN_2GHZ_BSW_ATTEN) | SM((pModal) ? pModal->bswAtten[2] : pModal4k->bswAtten[2], AR_PHY_GAIN_2GHZ_BSW_ATTEN)); + } } OS_REG_RMW_FIELD(ah, AR_PHY_GAIN_2GHZ, AR_PHY_GAIN_2GHZ_BSW_MARGIN, (pModal) ? pModal->bswMargin[0] : pModal4k->bswMargin[0]); @@ -1440,10 +1465,7 @@ ar5416SetPowerPerRateTable(struct ath_ha pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[1]), pEepData->modalHeader[IEEE80211_IS_CHAN_2GHZ(chan)].antennaGainCh[2]); else - twiceLargestAntenna = AH_MAX(AH_MAX( - pEepData4k->modalHeader.antennaGainCh[0], - pEepData4k->modalHeader.antennaGainCh[1]), - pEepData4k->modalHeader.antennaGainCh[2]); + twiceLargestAntenna = pEepData4k->modalHeader.antennaGainCh[0]; #if 0 /* Turn it back on if we need to calculate per chain antenna gain reduction */ /* Use only if the expected gain > 6dbi */ @@ -1577,15 +1599,15 @@ ar5416SetPowerPerRateTable(struct ath_ha freq = centers.ctl_center; } - ctlIndex = (pEepData) ? pEepData->ctlIndex[0] : - pEepData4k->ctlIndex[0]; /* walk through each CTL index stored in EEPROM */ - for (i = 0; (i < numctls) && ctlIndex; i++) { + for (i = 0; i < numctls; i++) { uint16_t twiceMinEdgePower; CAL_CTL_EDGES *ctlEdge; ctlIndex = (pEepData) ? pEepData->ctlIndex[i] : pEepData4k->ctlIndex[i]; + if (!ctlIndex) + break; /* compare test group from regulatory channel list with test mode from pCtlMode list */ if ((((cfgCtl & ~CTL_MODE_M) | (pCtlMode[ctlMode] & CTL_MODE_M)) == ctlIndex) || @@ -1943,7 +1965,7 @@ ar5416SetPowerCalTable(struct ath_hal *a SM(xpdGainValues[1], AR_PHY_TPCRG1_PD_GAIN_2) | SM(xpdGainValues[2], AR_PHY_TPCRG1_PD_GAIN_3)); for (i = 0; i < AR5416_MAX_CHAINS; i++) { - if (AR_SREV_KITE(ah) && i >= AR5416_4K_MAX_CHAINS) break; +// if (AR_SREV_KITE(ah) && i >= AR5416_4K_MAX_CHAINS) break; if (AR_SREV_OWL_20_OR_LATER(ah) && ( AH5416(ah)->ah_rx_chainmask == 0x5 || AH5416(ah)->ah_tx_chainmask == 0x5) && (i != 0)) { /* Regs are swapped from chain 2 to 1 for 5416 2_0 with @@ -1981,7 +2003,6 @@ ar5416SetPowerCalTable(struct ath_hal *a * negative or greater than 0. Need to offset the power * values by the amount of minPower for griffin */ - OS_REG_WRITE(ah, AR_PHY_TPCRG5 + regChainOffset, SM(pdGainOverlap_t2, AR_PHY_TPCRG5_PD_GAIN_OVERLAP) | SM(gainBoundaries[0], AR_PHY_TPCRG5_PD_GAIN_BOUNDARY_1) | @@ -2149,7 +2170,10 @@ ar5416GetGainBoundariesAndPdadcs(struct /* Find starting index for this pdGain */ if (i == 0) { - ss = 0; /* for the first pdGain, start from index 0 */ + if (AR_SREV_MERLIN_10_OR_LATER(ah)) + ss = (int16_t)(0 - (minPwrT4[i] / 2)); + else + ss = 0; /* for the first pdGain, start from index 0 */ } else { /* need overlap entries extrapolated below. */ ss = (int16_t)((pPdGainBoundaries[i-1] - (minPwrT4[i] / 2)) - tPdGainOverlap + 1 + minDelta); @@ -2165,7 +2189,7 @@ ar5416GetGainBoundariesAndPdadcs(struct ss++; } - sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 +1); + sizeCurrVpdTable = (uint8_t)((maxPwrT4[i] - minPwrT4[i]) / 2 + 1); tgtIndex = (uint8_t)(pPdGainBoundaries[i] + tPdGainOverlap - (minPwrT4[i] / 2)); maxIndex = (tgtIndex < sizeCurrVpdTable) ? tgtIndex : sizeCurrVpdTable; @@ -2314,13 +2338,20 @@ ar5416Set11nRegs(struct ath_hal *ah, con { uint32_t phymode; HAL_HT_MACMODE macmode; /* MAC - 20/40 mode */ + uint32_t dacFifo; if (!IEEE80211_IS_CHAN_HT(chan)) return; + if (AR_SREV_KITE_10_OR_LATER(ah)) + dacFifo = OS_REG_READ(ah, AR_PHY_TURBO) + & AR_PHY_FC_ENABLE_DAC_FIFO; + else + dacFifo = 0; + /* Enable 11n HT, 20 MHz */ phymode = AR_PHY_FC_HT_EN | AR_PHY_FC_SHORT_GI_40 - | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH; + | AR_PHY_FC_SINGLE_HT_LTF1 | AR_PHY_FC_WALSH | dacFifo; /* Configure baseband for dynamic 20/40 operation */ if (IEEE80211_IS_CHAN_HT40(chan)) { Modified: head/sys/dev/ath/ath_hal/ar5416/ar5416phy.h ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar5416phy.h Mon Feb 8 20:04:16 2010 (r203681) +++ head/sys/dev/ath/ath_hal/ar5416/ar5416phy.h Mon Feb 8 20:12:01 2010 (r203682) @@ -48,6 +48,7 @@ #define AR_PHY_FC_SHORT_GI_40 0x00000080 /* allow short GI for HT 40 */ #define AR_PHY_FC_WALSH 0x00000100 /* walsh spatial spreading for 2 chains,2 streams TX */ #define AR_PHY_FC_SINGLE_HT_LTF1 0x00000200 /* single length (4us) 1st HT long training symbol */ +#define AR_PHY_FC_ENABLE_DAC_FIFO 0x00000800 #define AR_PHY_TIMING2 0x9810 /* Timing Control 2 */ #define AR_PHY_TIMING2_USE_FORCE 0x00001000 @@ -78,6 +79,20 @@ #define AR_PHY_GAIN_2GHZ_BSW_ATTEN 0x0000001F #define AR_PHY_GAIN_2GHZ_BSW_ATTEN_S 0 +#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN 0x003E0000 +#define AR_PHY_GAIN_2GHZ_XATTEN2_MARGIN_S 17 +#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN 0x0001F000 +#define AR_PHY_GAIN_2GHZ_XATTEN1_MARGIN_S 12 +#define AR_PHY_GAIN_2GHZ_XATTEN2_DB 0x00000FC0 +#define AR_PHY_GAIN_2GHZ_XATTEN2_DB_S 6 +#define AR_PHY_GAIN_2GHZ_XATTEN1_DB 0x0000003F +#define AR_PHY_GAIN_2GHZ_XATTEN1_DB_S 0 + +#define AR9280_PHY_RXGAIN_TXRX_ATTEN 0x00003F80 +#define AR9280_PHY_RXGAIN_TXRX_ATTEN_S 7 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN 0x001FC000 +#define AR9280_PHY_RXGAIN_TXRX_MARGIN_S 14 + #define AR_PHY_EXT_CCA 0x99bc #define AR_PHY_EXT_CCA_CYCPWR_THR1 0x0000FE00 #define AR_PHY_EXT_CCA_CYCPWR_THR1_S 9 Modified: head/sys/dev/ath/ath_hal/ar5416/ar9280.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar9280.c Mon Feb 8 20:04:16 2010 (r203681) +++ head/sys/dev/ath/ath_hal/ar5416/ar9280.c Mon Feb 8 20:12:01 2010 (r203682) @@ -277,12 +277,15 @@ ar9280GetNoiseFloor(struct ath_hal *ah, "NF calibrated [ctl] [chain 0] is %d\n", nf); nfarray[0] = nf; - nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), AR9280_PHY_CH1_MINCCA_PWR); - if (nf & 0x100) - nf = 0 - ((nf ^ 0x1ff) + 1); - HALDEBUG(ah, HAL_DEBUG_NFCAL, - "NF calibrated [ctl] [chain 1] is %d\n", nf); - nfarray[1] = nf; + if (!AR_SREV_KITE(ah)) { + nf = MS(OS_REG_READ(ah, AR_PHY_CH1_CCA), + AR9280_PHY_CH1_MINCCA_PWR); + if (nf & 0x100) + nf = 0 - ((nf ^ 0x1ff) + 1); + HALDEBUG(ah, HAL_DEBUG_NFCAL, + "NF calibrated [ctl] [chain 1] is %d\n", nf); + nfarray[1] = nf; + } nf = MS(OS_REG_READ(ah, AR_PHY_EXT_CCA), AR9280_PHY_EXT_MINCCA_PWR); if (nf & 0x100) @@ -291,12 +294,15 @@ ar9280GetNoiseFloor(struct ath_hal *ah, "NF calibrated [ext] [chain 0] is %d\n", nf); nfarray[3] = nf; - nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), AR9280_PHY_CH1_EXT_MINCCA_PWR); - if (nf & 0x100) + if (AR_SREV_KITE(ah)) { + nf = MS(OS_REG_READ(ah, AR_PHY_CH1_EXT_CCA), + AR9280_PHY_CH1_EXT_MINCCA_PWR); + if (nf & 0x100) nf = 0 - ((nf ^ 0x1ff) + 1); - HALDEBUG(ah, HAL_DEBUG_NFCAL, - "NF calibrated [ext] [chain 1] is %d\n", nf); - nfarray[4] = nf; + HALDEBUG(ah, HAL_DEBUG_NFCAL, + "NF calibrated [ext] [chain 1] is %d\n", nf); + nfarray[4] = nf; + } } /* Modified: head/sys/dev/ath/ath_hal/ar5416/ar9280.h ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar9280.h Mon Feb 8 20:04:16 2010 (r203681) +++ head/sys/dev/ath/ath_hal/ar5416/ar9280.h Mon Feb 8 20:12:01 2010 (r203682) @@ -30,7 +30,9 @@ struct ath_hal_9280 { #define AH9280(_ah) ((struct ath_hal_9280 *)(_ah)) #define AR9280_DEFAULT_RXCHAINMASK 3 +#define AR9285_DEFAULT_RXCHAINMASK 1 #define AR9280_DEFAULT_TXCHAINMASK 1 +#define AR9285_DEFAULT_TXCHAINMASK 1 HAL_BOOL ar9280RfAttach(struct ath_hal *, HAL_STATUS *); Modified: head/sys/dev/ath/ath_hal/ar5416/ar9280_attach.c ============================================================================== --- head/sys/dev/ath/ath_hal/ar5416/ar9280_attach.c Mon Feb 8 20:04:16 2010 (r203681) +++ head/sys/dev/ath/ath_hal/ar5416/ar9280_attach.c Mon Feb 8 20:12:01 2010 (r203682) @@ -123,6 +123,10 @@ ar9280Attach(uint16_t devid, HAL_SOFTC s AH5416(ah)->ah_writeIni = ar9280WriteIni; AH5416(ah)->ah_rx_chainmask = AR9280_DEFAULT_RXCHAINMASK; AH5416(ah)->ah_tx_chainmask = AR9280_DEFAULT_TXCHAINMASK; + if (AR_SREV_KITE(ah)) { + AH5416(ah)->ah_rx_chainmask = AR9285_DEFAULT_RXCHAINMASK; + AH5416(ah)->ah_tx_chainmask = AR9285_DEFAULT_TXCHAINMASK; + } if (!ar5416SetResetReg(ah, HAL_RESET_POWER_ON)) { /* reset chip */