From owner-cvs-src-old@FreeBSD.ORG Fri May 1 17:06:10 2009 Return-Path: Delivered-To: cvs-src-old@freebsd.org Received: from mx1.freebsd.org (mx1.freebsd.org [IPv6:2001:4f8:fff6::34]) by hub.freebsd.org (Postfix) with ESMTP id 8DE2B106564A for ; Fri, 1 May 2009 17:06:10 +0000 (UTC) (envelope-from mav@FreeBSD.org) Received: from repoman.freebsd.org (repoman.freebsd.org [IPv6:2001:4f8:fff6::29]) by mx1.freebsd.org (Postfix) with ESMTP id 7A4C08FC14 for ; Fri, 1 May 2009 17:06:10 +0000 (UTC) (envelope-from mav@FreeBSD.org) Received: from repoman.freebsd.org (localhost [127.0.0.1]) by repoman.freebsd.org (8.14.3/8.14.3) with ESMTP id n41H6ASX089106 for ; Fri, 1 May 2009 17:06:10 GMT (envelope-from mav@repoman.freebsd.org) Received: (from svn2cvs@localhost) by repoman.freebsd.org (8.14.3/8.14.3/Submit) id n41H6AnK089105 for cvs-src-old@freebsd.org; Fri, 1 May 2009 17:06:10 GMT (envelope-from mav@repoman.freebsd.org) Message-Id: <200905011706.n41H6AnK089105@repoman.freebsd.org> X-Authentication-Warning: repoman.freebsd.org: svn2cvs set sender to mav@repoman.freebsd.org using -f From: Alexander Motin Date: Fri, 1 May 2009 17:05:49 +0000 (UTC) To: cvs-src-old@freebsd.org X-FreeBSD-CVS-Branch: HEAD Subject: cvs commit: src/sys/amd64/amd64 local_apic.c src/sys/i386/i386 local_apic.c X-BeenThere: cvs-src-old@freebsd.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: **OBSOLETE** CVS commit messages for the src tree List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 01 May 2009 17:06:10 -0000 mav 2009-05-01 17:05:49 UTC FreeBSD src repository Modified files: sys/amd64/amd64 local_apic.c sys/i386/i386 local_apic.c Log: SVN rev 191720 on 2009-05-01 17:05:49Z by mav Use value -1 instead of 0 for marking unused APIC vectors. This fixes IRQ0 routing on LAPIC-enabled systems. Add hint.apic.0.clock tunable. Setting it 0 disables using LAPIC timers as hard-/stat-/profclock sources falling back to using i8254 and rtc timers. On modern CPUs LAPIC is a part of CPU core which is shutting down when CPU enters C3 or deeper power state. It makes no problems for interrupt processing, as chipset wakes up CPU on interrupt triggering. But entering C3 state kills LAPIC timer and freezes system time, making C3 and deeper states practically unusable. Using i8254 timer allows to avoid this problem. By using i8254 timer my T7700 C2D CPU with UP kernel successfully enters C3 state, saving more then a Watt of total idle power (>10%) in addition to all other power-saving techniques. This technique is not working for SMP yet, as only one CPU receives timer interrupts. But I think that problem could be fixed by forwarding interrupts to other CPUs with IPI. Revision Changes Path 1.53 +11 -5 src/sys/amd64/amd64/local_apic.c 1.56 +11 -5 src/sys/i386/i386/local_apic.c