From owner-freebsd-smp Tue Jun 22 9: 6:31 1999 Delivered-To: freebsd-smp@freebsd.org Received: from thor.tvol.net (mail.tvol.com [38.219.83.4]) by hub.freebsd.org (Postfix) with ESMTP id AAB8714C81 for ; Tue, 22 Jun 1999 09:06:26 -0700 (PDT) (envelope-from agrosky@wgate.com) Received: from dadu.eng.tvol.net (dadu.eng.tvol.net [10.32.2.13]) by thor.tvol.net (8.8.8/8.8.3) with SMTP id MAA07030; Tue, 22 Jun 1999 12:11:49 -0400 (EDT) Date: Tue, 22 Jun 1999 12:04:12 -0400 (EDT) From: Aaron Grosky X-Sender: asg@dadu.eng.tvol.net Reply-To: Aaron Grosky To: Richard Cownie Cc: freebsd-smp@FreeBSD.ORG Subject: Re: SMP, 4GB RAM, 4x CPU In-Reply-To: <99062211111300.27479@par28.ma.ikos.com> Message-ID: MIME-Version: 1.0 Content-Type: TEXT/PLAIN; charset=US-ASCII Sender: owner-freebsd-smp@FreeBSD.ORG Precedence: bulk X-Loop: FreeBSD.org On Tue, 22 Jun 1999, Richard Cownie wrote: > On Mon, 21 Jun 1999, Terry Lambert wrote: > > DEC (used to; haven't checked lately) have instruction scheduling > > code up for download on gatekeeper.dec.com. From memory, running > > it as an assembler preprocessor was pretty trivial. Of course, > > DEC may have advanced the technology without posting new code, so > > YMMV... > > To expose enough parallelism to get a good instruction schedule, > you probably need to do a lot of stuff earlier in the compilation, > e.g. loop unrolling, traversing the expression tree in a different > order for code-generation/register-allocation. In particular, > once the register allocation is cast in stone you don't have very > much freedom to re-order instructions. So I doubt that the > assembler pre-processor makes a big difference - if you want > good performance from the Alpha (and why else would you want > an Alpha ?) the DEC compiler is probably the only game in town. > > Unless anyone's tried the assembler scheduler and has figures to > suggest otherwise ? > > I notice that egcs (soon to be gcc-2.95) has a bunch of new > instruction-scheduling stuff, maybe this will do better than the > old gcc. '70s and early '80s vintage C compilers used an assembler optimizer step (input was ASCII assembly language, output was ASCII assembly language). This optimizer was able to reassign registers and rearrange code to achieve better use of registers and remove redundant memory accesses. Such an optimizer could be used to optimize RISC code (and ever *86 code), or analysis of this sort could even be build into the assembler (though then it would no longer be an assembler). In saying this, I do not disagree with Richard that doing the analysis earlier cannot achieve better optimization. I only point out that assigning the registers does not prevent major code movement nor register reassignment. Aaron Grosky agrosky@wgate.com WorldGate Communications "Internet TV Over Cable" 3220 Tillman Drive 215-633-5125 Bensalem, PA 19020 215-633-9590 (FAX) To Unsubscribe: send mail to majordomo@FreeBSD.org with "unsubscribe freebsd-smp" in the body of the message