From owner-freebsd-hackers Wed Jan 8 12:42:56 1997 Return-Path: Received: (from root@localhost) by freefall.freebsd.org (8.8.4/8.8.4) id MAA28251 for hackers-outgoing; Wed, 8 Jan 1997 12:42:56 -0800 (PST) Received: from smtp-gw01.ny.us.ibm.net (smtp-gw01.ny.us.ibm.net [165.87.194.252]) by freefall.freebsd.org (8.8.4/8.8.4) with SMTP id MAA28237 for ; Wed, 8 Jan 1997 12:42:51 -0800 (PST) Received: (from uucp@localhost) by smtp-gw01.ny.us.ibm.net (8.6.9/8.6.9) id UAA123445; Wed, 8 Jan 1997 20:41:33 GMT Message-Id: <199701082041.UAA123445@smtp-gw01.ny.us.ibm.net> Received: from slip166-72-229-214.va.us.ibm.net(166.72.229.214) by smtp-gw01.ny.us.ibm.net via smap (V1.3mjr) id smaAO4DM2; Wed Jan 8 20:41:16 1997 Reply-To: From: "Steve Sims" To: "Terry Lambert" Cc: , Subject: Re: Bounce Buffers and CCD Date: Wed, 8 Jan 1997 15:27:44 -0500 X-MSMail-Priority: Normal X-Priority: 3 X-Mailer: Microsoft Internet Mail 4.70.1155 MIME-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Sender: owner-hackers@FreeBSD.ORG X-Loop: FreeBSD.org Precedence: bulk > From: Terry Lambert > > >> (Terry, I hope I haven't quoted you out of context, but I'm here to tell > > >> ya': BOUNCE-BUFFERS is a MANDATORY option for >16M systems, at least on > > >> 3.0-CURRENT with my mo-bo having PCI, ISA and VESA!) > > > > > > Then it's not required AND it's broken. 8-(. > > > > > > Bounce conditions are supposed to be autodetected. > > > > Would that it were true.... > > > Bounce buffers should be implied by the 1542 driver, automagically. If > they are not, then the driver is broken; I would guess "recently". Settled: The driver looks to be broken. I'll sup -CURRENT and see if it's been magically fixed, if not, how to proceed with tracking this down; who's the keeper of the 1542 code? > It's not PCI/VESA, so it's 24 (standard for ISA). Means the DMA target > has to be in the low 16M, and if it isn't it needs to be "bounced". > This is determined by knowing that it's an AHA1542 driver (ISA DMA > bus master) and comparing the address to see if it's above 16M. > > > "Supposed" being the operative term here... ;-) > > "Is handled as far as I know for non-broken hardware that meets the > bus specifications as ratified as accepted standards". > > In other words, making NiCE HiNT chipset machines work is out of scope > (but possible -- see previous postings for this subject). I shudder at the recollection of *that* brain-damaged chipset! ...sjs...