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Date:      Wed, 23 May 2001 12:45:22 -0500
From:      Jonathan Lemon <jlemon@flugsvamp.com>
To:        Parag Patel <parag@codegen.com>
Cc:        Jonathan Lemon <jlemon@flugsvamp.com>, mike@sentex.net, stable@FreeBSD.ORG
Subject:   Re: Continuing ahc problems - also cause fxp failure
Message-ID:  <20010523124522.J68487@prism.flugsvamp.com>
In-Reply-To: <4555.990639197@tenor.codegen.com>
References:  <jlemon@flugsvamp.com> <4555.990639197@tenor.codegen.com>

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On Wed, May 23, 2001 at 10:33:17AM -0700, Parag Patel wrote:
> In message <200105231527.f4NFRGs46131@prism.flugsvamp.com>, Jonathan Lemon writes:
> >
> >What's interesting to note, is that both Matt and Vladislav's 
> >systems are using the same RCC chipset:
> >   <ServerWorks NB6635 3.0LE host to PCI bridge>
> [...]
> >Is anyone else running fxp + ahc combination on this chipset?
> 
> I'm currently working (for a client) on fxp drivers for VxWorks/x86 for
> an STL2 motherboard with this chipset and have been running into
> interesting problems as well.
> 
> I get occasional lock-ups and other screwy behavior under extremely
> heavy load (generated by SmartBits) when there is also a VPN accelerator
> plugged in to the system.

I was just playing with the driver here on an 815E system.  I was 
able to get an SCB timeout when I subjected the network to heavy 
traffic as well as intensive IDE disk activity.  When the SCB timeout
happens, the PCI status register had the 'received master abort' error
bit set.  Perhaps the chip was denied access to the PCI bus?  This 
is not a serverworks system, btw.


> Some of these problems could be considered bugs in my driver.  :)  It
> turns out that under heavy loads, the chip may not update its SCB status
> register soon enough after it accepts a new RU or CU command but has
> already begun the new command.  If either unit is restarted too soon,
> double-transmits/receives can occur, out of or into buffers that have
> already been freed or used for other purposes.

Check the manual.  The SCB status register is not updated immediately
in response to SCB commands.  However, the SCB command register should
be cleared as soon as the chip accepts (but not necessarily executes) 
the command.

--
Jonathan

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